M37632EFFP#U2 Renesas Electronics America, M37632EFFP#U2 Datasheet
M37632EFFP#U2
Specifications of M37632EFFP#U2
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M37632EFFP#U2 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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Family 8 Software Manual RENESAS MCU All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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REVISION HISTORY Rev. Date Page 1.00 – First edition issued Aug 29, 1997 2.00 – Changed to the RENESAS style. Nov 14, 2006 “Preface” is changed to “Using This Manual”. 4 2.5 Processor Status Register: Description added. 26 3.2 Instruction ...
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This software manual is written for the 740 Family. It applies to all microcomputers integrating the 740 Family CPU core. The reader of this manual is assumed to have a basic knowledge of electrical circuits, logic circuits, and microcomputers. 740 ...
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Table of contents CHAPTER 1. OVERVIEW ............................................................................................ 1 CHAPTER 2. CENTRAL PROCESSING UNIT (CPU) ............................................. 2 2.1 Accumulator (A) ........................................................................................................................ 2 2.2 Index Register X (X), Index Register Y (Y) ........................................................................ 2 2.3 Stack Pointer (S) ...................................................................................................................... 3 2.4 Program ...
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APPENDIX 1. Instruction Cycles in each Addressing Mode ........................ 112 APPENDIX 2. 740 Family Machine Language Instruction Table .................. 178 APPENDIX 3. 740 Family list of Instruction Codes ........................................ 184 <Addressing Mode> Immediate .................................. 7 Accumulator .............................. 8 Zero Page ...
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OVERVIEW 1. OVERVIEW The distinctive features of the CMOS 8-bit microcomputers 740 Family’s software are described below efficient instruction set and many addressing modes allow the effective use of ROM. 2) The same bit management, test, and branch ...
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CENTRAL PROCESSING UNIT 2. CENTRAL PROCESSING UNIT (CPU) Six main registers are built into the CPU of the 740 Family. The Program Counter (PC sixteen-bit register; however, the Accumulator (A), Index Register X (X), Index Register Y (Y), ...
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CENTRAL PROCESSING UNIT 2.3 Stack Pointer (S) The Stack Pointer is an eight-bit register used for generating interrupts and calling subroutines. When an interrupt is received, the following procedure is performed automatically in the indicated sequence: (1) The contents of ...
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CENTRAL PROCESSING UNIT 2.4 Program Counter (PC) The Program Counter is a sixteen-bit counter consisting of PC eight-bit registers. The contetnts of the Program Counter indicates the address which an instruction to be executed next is stored. The 740 Family ...
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CENTRAL PROCESSING UNIT [ X modified operation mode flag T ] ----------------------- Bit 5 This flag determines whether arithmetic operations are performed via the Accumulator or directly on a memory location. When the flag is set to “0”, arithmetic operations ...
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INSTRUCTIONS 3. INSTRUCTIONS 3.1 Addressing Mode The 740 Family has 19 addressing modes and a powerful memory access capability. When extracting data required for arithmetic and logic operations from memory or when storing the results of such operations in memory, ...
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INSTRUCTIONS Immediate Addressing mode : Specifies the Operand as the data for the instruction. Function : ADC, AND, CMP, CPX, CPY, EOR, LDA, LDX, LDY, Instructions : ORA, SBC Example : Mnemonic (A) ← ( Rev.2.00 ...
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INSTRUCTIONS Addressing mode : Accumulator Function : Specifies the contents of the Accumulator as the data for the instruction. Instructions : ASL, DEC, INC, LSR, ROL, ROR Example : Mnemonic ...
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INSTRUCTIONS Zero Page Addressing mode : Specifies the contents in a Zero Page memory Function : location as the data for the instruction. The address in the Zero Page memory location is determined by using Operand as the low-order byte ...
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INSTRUCTIONS Zero Page X Addressing mode : Specified the contents in a Zero Page memory Function : location as the data for the instruction. The address in the Zero Page memory location is determined by the following: (a) Operand and ...
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INSTRUCTIONS Zero Page Y Addressing mode : Specifies the contents in a Zero Page memory Function : location as the data for the instruction. The address in the Zero Page memory location is determined by the following: (a) Operand and ...
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INSTRUCTIONS Addressing mode : Absolute Function : Specifies the contents in a memory location as the data for the instruction. The address in the memory location is determined by using Operand I as the low- order byte of the address ...
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INSTRUCTIONS Absolute X Addressing mode : Specifies the contents in a memory location as the Function : data for the instruction. The address in the memory location is determined by the following: (a) Operand I is used as the low-order ...
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INSTRUCTIONS Absolute Y Addressing mode : Specifies the contents in a memory location as the Function : data for the instruction. The address in the memory location is determined by the following: (a) Operand I is used as the low-order ...
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INSTRUCTIONS Implied Addressing mode : Operates on a given register or the Accumulator, but Function : the address is always inherent in the instruction. BRK, CLC, CLD, CLI, CLT, CLV, DEX, DEY, INX, INY, Instructions : NOP, PHA, PHP, PLA, ...
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INSTRUCTIONS Addressing mode : Relative Function : Specifies the address in a memory location where the next Op-Code is located. When the branch condition is satisfied, Operand and the Program Counter are added. The result of this addition is the ...
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INSTRUCTIONS Indirect X Addressing mode : Specifies the contents in a memory location as the Function : data for the instruction. The address in the memory location is determined by the following: (a) A Zero Page memory location is determined ...
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INSTRUCTIONS Indirect Y Addressing mode : Specifies the contents in a memory location as the Function : data for the instruction. The address in the memory location is determined by the following: (a) The Operand is used the low-order byte ...
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INSTRUCTIONS Indirect Absolute Indirect Absolute Addressing mode : Specifies the address in a memory location as the Function : jump destination address. The address in the memory location is determined by the following: (a) Operand I is used as the ...
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INSTRUCTIONS Zero Page Indirect Zero Page Indirect Absolute Addressing mode : Specifies the address in a memory location as the Function : jump destination address. The address in the memory location is determined by the following: (a) Operand is used ...
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INSTRUCTIONS Addressing mode : Special Page Function : Specifies the address in a Special Page memory location as the jump destination address. The address in the Special Page memory location is determined by using Operand as the low-order byte of ...
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INSTRUCTIONS Zero Page Bit Addressing mode : Specifies one bit of the contents in a Zero Page Function : memory location as the data for the instruction. Operand is used as the low-order byte of the address in the Zero ...
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INSTRUCTIONS Accumulator Bit Accumulator Bit Addressing mode : Specifies one bit of the Accumulator as the data for Function : the instruction. The bit position is designated by the high-order three bits of the Op-Code. CLB, SEB ...
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INSTRUCTIONS Accumulator Bit Relative Accumulator Bit Relative Addressing mode : Specifies the address in a memory location where the Function : next Op-Code is located. The bit position is designated by the high-order three bits of the Op-Code. If the ...
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INSTRUCTIONS Zero Page Bit Relative Zero Page Bit Relative Addressing mode : Specifies the address of a memory location where the Function : next Op-Code is located. The bit position is designated by the high-order three bits of the Op-Code. ...
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INSTRUCTIONS 3.2 Instruction Set The 740 Family has 71 types of instructions. The detailed explanation of the instructions is presented in §3.3. Note that some instructions cannot be used for some products. 3.2.1 Data transfer instructions These instructions transfer the ...
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INSTRUCTIONS 3.2.2 Operating instruction The operating instructions include the operations of addition and subtraction, logic, comparison, rotation, and shift. The operating instructions are as follows: Instructions Add memory contents and C flag to Accumulator or memory ADC where is indicated ...
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INSTRUCTIONS 3.2.3 Bit managing instructions The bit managing instructions clear “0” or set “1” designated bits of the Accumulator or memory. Instructions Clear designated bit in the Accumulator or memory Bit CLB SEB Set designated bit in the Accumulator or ...
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INSTRUCTIONS 3.2.6 Interrupt instruction (Break instruction) This instruction causes a software interrupt. Instruction Interrupt BRK 3.2.7 Special instructions These special instructions control the oscillation and the internal clock. Instructions WIT Special STP 3.2.8 Other instruction Instruction Other NOP Rev.2.00 Nov ...
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INSTRUCTIONS 3.3 Description of instructions This section presents in detail the 740 Family instructions by arranging mnemonics of instruc- tions alphabetically and dividing each instruction essentially into one page. The heading of each page is a mnemonic. Operation, explanation and ...
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ADC When ( (A) ← (A) + (M) + (C) Operation : ( (M(X)) ← (M(X)) + (M) + (C) Function : When this instruction adds the contents M, C, and A; and ...
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AND When ( (A) ← (A) ∧ (M) Operation : ( (M(X)) ← (M(X)) ∧ (M) When this instruction transfers the contents of A and M Function : to the ALU which performs ...
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ASL Operation : ← C Function : This instruction shifts the content one bit to the left, with bit 0 always being set to 0 and bit always being contained ...
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BBC When (Mi) or (Ai (PC) ← (PC REL Operation : (Mi) or (Ai (PC) ← (PC This instruction tests the designated bit and takes Function ...
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When (Mi) or (Ai (PC) ← (PC REL Operation : (Mi) or (Ai (PC) ← (PC This instruction tests the designated bit i of the ...
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BCC When ( (PC) ← (PC REL Operation : ( (PC) ← (PC This instruction takes a branch to the appointed address Function : 0. The branch address ...
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BCS When ( (PC) ← (PC REL Operation : ( (PC) ← (PC This instruction takes a branch to the appointed address Function : 1. The branch address ...
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BEQ When ( (PC) ← (PC REL Operation : ( (PC) ← (PC This instruction takes a branch to the appointed address when Function : The branch address ...
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BIT BIT TEST (A) ∧ (M) Operation : This instruction takes a bit-wise logical AND of A and M Function : contents; however, the contents of A and M are not modified. The contents are changed, ...
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BMI B When ( (PC) ← (PC REL Operation : ( (PC) ← (PC Function : This instruction takes a branch to the appointed address when The branch ...
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BNE When ( (PC) ← (PC REL Operation : ( (PC) ← (PC This instruction takes a branch to the appointed address Function : 0. The branch address ...
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BPL When ( (PC) ← (PC REL Operation : ( (PC) ← (PC This instruction takes a branch to the appointed address Function : 0. The branch address ...
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BRA (PC) ← (PC REL Operation : This instruction branches to the appointed address. The branch Function : address is specified by a relative address. No change Status flag : Addressing mode Statement ∆BRA∆$hhll Relative Note: rr ...
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BRK (B) ← 1 Operation : (PC) ← (PC (M(S)) ← (PC (S) ← (S) – 1 (M(S)) ← (PC (S) ← (S) – 1 (M(S)) ← (PS) (S) ← (S) – 1 (I) ← 1 (PC) ← ...
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BVC B RANCH ON O When ( (PC) ← (PC REL Operation : ( (PC) ← (PC Function : This instruction takes a branch to the appointed address ...
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BVS B When ( (PC) ← (PC REL Operation : ( (PC) ← (PC Function : This instruction takes a branch to the appointed address when The branch ...
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CLB (Ai) ← Operation : (Mi) ← 0 Function : This instruction clears the designated bit Status flag : No change Statement Addressing mode ∆CLB∆i,A Accumulator bit ∆CLB∆i,$zz Zero page bit Rev.2.00 Nov ...
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CLC (C) ← 0 Operation : Function : This instruction clears C. Status flag change change change change change No change ...
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CLD (D) ← 0 Operation : This instruction clears D. Function : No change Status flag change change change change change Z ...
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CLI CL EAR (I) ← 0 Operation : Function : This instruction clears I. Status flag change No change change change change Z ...
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CLT (T) ← 0 Operation : This instruction clears T. Function : No change Status flag change change change change change Z ...
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CLV (V) ← 0 Operation : This instruction clears V. Function : change Status flag change change No change change ...
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CMP When ( (A) – (M) Operation : ( (M(X)) – (M) When this instruction subtracts the contents of M from Function : the contents of A. The result is not stored and ...
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COM (M) ← (M) Operation : This instruction takes the one’s complement of the contents of Function : M and stores the result when bit 7 of the after the operation; Status ...
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CPX ARE MEMORY AND INDEX REGISTER Operation : (X) – (M) Function : This instruction subtracts the contents of M from the contents of X. The result is not stored and the contents of X and M ...
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CPY ARE MEMORY AND INDEX REGISTER (Y) – (M) Operation : This instruction subtracts the contents of M from the contents of Function : Y. The result is not stored and the contents of Y and M ...
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DEC (A) ← (A) – Operation : (M) ← (M) – 1 This instruction subtracts 1 from the contents Function : when bit after the addition; ...
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DEX DE CREMENT INDEX REGISTER (X) ← (X) – 1 Operation : This instruction subtracts one from the current contents of X. Function : Status flag when bit after the operation; otherwise ...
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DEY DE CREMENT INDEX REGISTER (Y) ← (Y) – 1 Operation : This instruction subtracts one from the current contents of Y. Function : Status flag when bit after the operation; otherwise ...
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DIV DIV IDE MEMORY BY ACCUMULATOR (A) ← (M(zz+(X)+1),M(zz+(X)) / (A) Operation : M(S) ← one’s complement of Remainder (S) ← (S) – 1 Function : Divides the 16-bit data in M(zz+(X)) (low-order byte) and M(zz+(X)+1) (high-order byte) by the ...
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EOR E XCLUSIVE When ( (A) ← (A) ∀ (M) Operation : ( (M(X)) ← (M(X)) ∀ (M) Function : When this instruction transfers the contents of the M and A to the ...
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INC (A) ← ( Operation : (M) ← ( This instruction adds one to the contents Function : when bit after the operation; otherwise N ...
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INX IN CREMENT INDEX REGISTER (X) ← ( Operation : Function : This instruction adds one to the contents of X. Status flag when bit after the operation; otherwise N ...
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INY IN CREMENT INDEX REGISTER (Y) ← ( Operation : Function : This instruction adds one to the contents of Y. Status flag when bit after the operation; otherwise N ...
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JMP When addressing mode is Operation : (a) Absolute, then (b) Indirect Absolute, then (c) Zero page Indirect Absolute, then This instruction jumps to the address designated by the Function : following three addressing modes: Absolute Indirect Absolute Zero Page ...
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(M(S)) ← (PC Operation : (S) ← (S) – 1 (M(S)) ← (PC (S) ← (S) – 1 After the above operations, if the addressing mode is (a) Absolute, then (b) Special page, then (c) Zero page ...
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LDA When ( (A) ← (M) Operation : ( (M(X)) ← (M) Function : When this instruction transfers the contents When this ...
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LDM L OAD IMMEDIATE (M) ← nn Operation : Function : This instruction loads the immediate value in M. Status flag : No change Addressing mode Statement ∆LDM∆#$nn,$zz Zero page Rev.2.00 Nov 14, 2006 page 68 of 185 REJ09B0322-0200 D ...
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LDX INDEX REGISTER (X) ← (M) Operation : This instruction loads the contents Function : when bit after the operation; otherwise N is Status flag ...
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LDY INDEX REGISTER (Y) ← (M) Operation : This instruction loads the contents Function : when bit after the operation; otherwise N is Status flag ...
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LSR Operation : → 0 This instruction shifts either one bit to the right such Function : that bit 7 of the result always is set to 0, and the bit 0 is stored ...
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MUL MUL TIPLY ACCUMULATOR AND MEMORY M(S) • (A) ← (A) Operation : (S) ← (S) – 1 Multiplies Accumulator with the memory specified by the Zero Function : Page X addressing mode and stores the high-order byte of the ...
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NOP (PC) ← (PC Operation : Function : This instruction adds one to the PC but does no other operation. Status flag : No change Addressing mode Statement ∆NOP Implied Rev.2.00 Nov 14, 2006 page 73 of 185 ...
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ORA OR When ( (A) ← (A) ∨ (M) Operation : ( (M(X)) ← (M(X)) ∨ (M) When this instruction transfers the contents of A and M Function : to the ALU which ...
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PHA P US (M(S)) ← (A) Operation : (S) ← (S) – 1 Function : This instruction pushes the contents the memory location designated by S, and decrements the contents one. Status flag : ...
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PHP (M(S)) ← (PS) Operation : (S) ← (S) – 1 Function : This instruction pushes the contents the memory loca- tion designated by S and decrements the contents one. ...
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PLA (S) ← ( Operation : (A) ← (M(S)) This instruction increments S by one and stores the contents of Function : the memory designated when ...
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PLP (S) ← ( Operation : (PS) ← (M(S)) Function : This instruction increments S by one and stores the contents of the memory location designated PS. Status flag : ...
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ROL Operation : b7 This instruction shifts either one bit left through Function : stored in bit 0 and bit 7 is stored when bit before ...
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ROR Operation : C This instruction shifts either one bit right through C. C Function : is stored in bit 7 and bit 0 is stored when ...
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RRF R Operation : b 7 This instruction rotates 4 bits of the M content to the right. Function : No change Status flag : Addressing mode Statement ∆RRF∆$zz Zero page Rev.2.00 Nov 14, 2006 page 81 of 185 REJ09B0322-0200 ...
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RTI (S) ← ( Operation : (PS) ← (M(S)) (S) ← ( ← (M(S)) (PC L (S) ← ( ← (M(S)) (PC H Function : This instruction increments S by one, and ...
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(S) ← ( Operation : ) ← (M(S)) (PC L (S) ← ( ← (M(S)) (PC H (PC) ← (PC Function : This instruction increments S by one and stores ...
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SBC When ( (A) ← (A) – (M) – (C) Operation : ( (M(X)) ← (M(X)) – (M) – (C) When this instruction subtracts the value of M and the Function : complement ...
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(Ai) ← Operation : (Mi) ← 1 This instruction sets the designated bit Function : No change Status flag: Addressing mode Statement ∆SEB∆i,A Accumulator bit ∆SEB∆i,$zz Zero page bit Rev.2.00 ...
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SEC (C) ← 1 Operation : This instruction sets C. Function : No change N : Status flag: No change change change change change change ...
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(D) ← 1 Operation : This instruction set D. Function : No change Status flag change change change change ...
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SEI SE (I) ← 1 Operation : This instruction sets I. Function : No change Status flag change change change change change ...
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SET (T) ← 1 Operation : This instruction sets T. Function : No change Status flag change change change change change Z ...
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STA ST ORE (M) ← (A) Operation : Function : This instruction stores the contents The contents of A does not change. Status flag: No change Addressing mode Statement ∆STA∆$zz Zero page ∆STA∆$zz,X Zero page X ...
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STP CPU ← Stand-by state (Oscillation stopped) Operation : This instruction resets the oscillation control F/F and the oscil- Function : lation stops. Reset or interrupt input is needed to wake up from this mode. No change Status flag: Addressing ...
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STX ST ORE INDEX REGISTER (M) ← (X) Operation : This instruction stores the contents The contents of Function : X does not change. No change Status flag: Statement Addressing mode ∆STX∆$zz Zero page ∆STX∆$zz,Y Zero ...
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STY ST ORE INDEX REGISTER (M) ← (Y) Operation : This instruction stores the contents Function : The contents of Y does not change. No change Status flag: Addressing mode Statement ∆STY∆$zz Zero page ∆STY∆$zz,X Zero ...
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TAX T RANSFER (X) ← (A) Operation : Function : This instruction stores the contents The contents of A does not change. Status flag when bit after the ...
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TAY T RANSFER (Y) ← (A) Operation : This instruction stores the contents The contents of Function : A does not change when bit after the operation; otherwise N is ...
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TST T E Operation : ( Function : This instruction tests whether the contents of M are “0” or not and modifies the N and Z. Status flag when bit 7 of ...
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TSX T S RANSFER (X) ← (S) Operation : This instruction transfers the contents Function : Status flag when bit after the operation; otherwise ...
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TXA T RANSFER INDEX REGISTER (A) ← (X) Operation : This instruction stores the contents Function : when bit after the operation; otherwise Status flag: 0. ...
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TXS T RANSFER INDEX REGISTER (S) ← (X) Operation : This instruction stores the contents Function : No change Status flag Addressing mode Statement ∆TXS Implied Rev.2.00 Nov 14, 2006 page 99 of 185 REJ09B0322-0200 X ...
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TYA T RANSFER INDEX REGISTER (A) ← (Y) Operation : Function : This instruction stores the contents Status flag when bit after the operation; otherwise ...
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WIT CPU ← Wait state Operation : Function : The WIT instruction stops the internal clock but the oscillation of the oscillation circuit is not stopped. Reset or interrupt input is needed to wake up from this mode. Status flag ...
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INSTRUCTIONS Instructions Related to Interrupt Processing and Subroutine Processing 3.4 Instructions Related to Interrupt Handling and Subroutine Processing 3.4.1 Instructions Related to Interrupt Handling When an interrupt is accepted, the contents of the processor status register are pushed onto the ...
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INSTRUCTIONS Instructions Related to Interrupt Processing and Subroutine Processing (4) Interrupt Control within Interrupt Routines After an interrupt is accepted and execution of the interrupt routine begins, the interrupt disable flag (I) is set to “1” automatically to prevent multiple ...
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INSTRUCTIONS Instructions Related to Interrupt Processing and Subroutine Processing Push return address M(S) ← ( onto stack (S) ← (S) – 1 M(S) ← ( (S) ← (S) – 1 Subroutine Execute RTS instruction (S) ← ...
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NOTES ON USE The information below applies to the entire 740 Family. Please refer conjunction with the usage notes of each specific product model. 4.1 Notes on input and output ports 4.1.1 Notes in standby state ...
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NOTES ON USE 4.2 Termination of unused pins At the termination of unused pins, perform wiring at the shortest possible distance ( less) from microcomputer pins. With regard to an effects on the system, thoroughly perform system evaluation ...
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Notes on interrupts 4.3.1 Setting for interrupt request bit and interrupt enable bit To set an interrupt request bit and an interrupt enable bit for interrupts, execute as the following sequence: Clear an interrupt request bit to “0” (no ...
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NOTES ON USE 4.3.3 Distinction of interrupt request bit When executing the BBC or BBS instruction to an interrupt request (request distinguish) bit of an interrupt request register (interrupt request distinguish register) immediately after this bit is set to “0”, ...
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Notes on programming 4.4.1 Processor Status Register (1) Initialization of Processor Status Register Flags which affect program execution must be initialized after a reset. In particular essential to initialize the T and D flags because they have ...
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NOTES ON USE 4.4.2 BRK instruction (1) Method detecting interrupt source It can be detected that the BRK instruction interrupt event or the least priority interrupt event by referring the stored B flag state. Refer the stored B flag state ...
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Status flags in decimal mode When decimal mode is selected (D = 1), the values of three of the flags in the status register (the flags N, V, and Z) are invalid after a ADC or SBC instruction is ...
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APPENDIX 1 Instruction Cycles in each Addressing Mode APPENDIX 1. Instruction Cycles in each Addressing Mode Clock φ controls the system timing of 740 Family. The SYNC signal and the value of PC (Program Counter) are output in every instruction ...
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Instructions : ∆CLD ∆CLI ∆CLT ∆CLV ∆DEX ∆DEY ∆INX ∆INY ∆NOP Byte length : 1 Cycle number : 2 Timing : φ SYNC R ADDR PC DATA ADDR PC H ADDR /DATA Rev.2.00 Nov ...
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Instruction : Byte length : 1 Cycle number : 7 Timing : φ SYNC R ADDR Op - DATA code ADDR ADDR ...
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Instructions : ∆WIT Byte length : 1 Timing : φ SYNC R ADDR PC DATA Op -code PC ADDR H H ADDR code /DATA Rev.2.00 Nov 14, 2006 ...
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Instruction : Byte length : 1 Cycle number : 6 Timing : φ φ φ φ ADDR H H ...
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Instruction : Byte length : 1 Cycle number : 6 Timing : φ φ φ φ ...
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Instructions : ∆PHP Byte length : 1 Cycle number : 3 Timing : φ SYNC R ADDR DATA ADDR H ADDR L PC /DATA Note: Some p roducts are “01” or content of SPS flag. Rev.2.00 Nov ...
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Instructions : ∆PLP Byte length : 1 Cycle number : 4 Timing : φ φ φ φ R ADDR P C DATA ...
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Instructions : ∆AND∆#$nn ∆CMP∆#$nn ∆CPX∆#$nn ∆CPY∆#$nn ∆EOR∆#$nn ∆LDA∆#$nn ∆LDX∆#$nn ∆LDY∆#$nn ∆ORA∆#$nn ∆SBC∆#$nn 2 Byte length : Cycle number : 2 Timing : φ φ φ φ SYNC R ...
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Instructions : ∆DEC ∆A ∆INC ∆A ∆LSR ∆A ∆ROL ∆A ∆ROR ∆A Byte length : 1 Cycle number : 2 Timing : φ SYNC R ADDR DATA ADDR PC H ADDR L PC /DATA Rev.2.00 Nov ...
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ACCUMULATOR BIT RELATIVE ∆BBC∆i,A,$hhll Instructions : ∆BBS∆i,A,$hhll Byte length : 2 (1) With no branch Cycle number : 4 Timing : φ SYNC R ADDR PC DATA Op -code ADDR ADDR ...
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ACCUMULATOR BIT RELATIVE ∆BBC∆i,A,$hhll Instructions : ∆BBS∆i,A,$hhll Byte length : 2 (2) With branch Cycle number : 6 Timing : φ φ φ φ DATA ...
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ACCUMULATOR BIT ∆CLB∆i,A Instructions : ∆SEB∆i,A Byte length : 1 Cycle number : 2 Timing : φ SYNC R ADDR DATA ADDR H ADDR L /DATA Rev.2.00 Nov 14, 2006 page 124 of 185 REJ09B0322-0200 PC+1 PC Invalid ...
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Instructions : ∆BBS∆i,$zz,$hhll Byte length : 3 (1) With no branch Cycle number : 5 Timing : φ SYNC R ADDR DATA PC ADDR H ADDR /DATA Rev.2.00 Nov 14, 2006 page 125 ...
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Instructions : ∆BBS∆i,$zz,$hhll Byte length : 3 (2) With branch Cycle number : 7 Timing : φ φ φ φ ADDR DATA O ...
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Instructions : ∆SEB∆i,$zz Byte length : 2 Cycle number : 5 Timing : φ SYNC R ADDR PC DATA ADDR H PC ADDR /DATA Rev.2.00 Nov 14, 2006 page 127 of 185 REJ09B0322-0200 ZERO ...
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Instructions : ∆AND ∆$zz ∆BIT ∆$zz ∆CMP ∆$zz ∆CPX ∆$zz ∆CPY ∆$zz ∆EOR ∆$zz ∆LDA ∆$zz ∆LDX ∆$zz ∆LDY ∆$zz ∆ORA ∆$zz ∆SBC ∆$zz ∆TST ∆$zz Byte length : 2 Cycle number : 3 Timing : φ ...
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Instructions : ∆COM ∆$zz ∆DEC ∆$zz ∆INC ∆$zz ∆LSR ∆$zz ∆ROL ∆$zz ∆ROR ∆$zz Byte length : 2 Cycle number : 5 Timing : φ SYNC R ADDR DATA ADDR PC H ADDR L PC ...
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Instruction : Byte length : 2 Cycle number : 8 Timing : φ SYNC R ADDR PC DATA Op -code ADDR ADDR ...
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Instruction : Byte length : 3 Cycle number : 4 Timing : φ SYNC R ADDR PC DATA PC ADDR H H ADDR code /DATA Rev.2.00 Nov 14, 2006 page 131 ...
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Instructions : ∆STX∆$zz ∆STY∆$zz Byte length : 2 Cycle number : 4 Timing : φ SYNC R ADDR DATA ADDR H ADDR L PC /DATA Rev.2.00 Nov 14, 2006 page 132 of 185 REJ09B0322-0200 ZERO PAGE PC ...
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Instruction : Byte length : 2 Cycle number : 15 Timing : φ φ φ φ ...
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Instruction : Byte length : 2 Cycle number : 16 Timing : φ φ φ φ ...
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Instructions : ∆DEC ∆$zz,X ∆INC ∆$zz,X ∆LSR ∆$zz,X ∆ROL ∆$zz,X ∆ROR∆$zz,X Byte length : 2 Cycle number : 6 Timing : φ SYNC R ADDR PC DATA ADDR H PC ADDR /DATA Rev.2.00 ...
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ZERO PAGE X, ZERO PAGE Y ∆ADC ∆$zz,X Instructions : ∆AND ∆$zz,X ∆CMP∆$zz,X ∆EOR ∆$zz,X ∆LDA ∆$zz,X ∆LDX ∆$zz,Y ∆LDY ∆$zz,X ∆ORA∆$zz,X ∆SBC ∆$zz,X Byte length : 2 Cycle number : 4 Timing : φ SYNC R ...
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ZERO PAGE X, ZERO PAGE Y ∆STA∆$zz,X Instructions : ∆STX∆$zz,Y ∆STY∆$zz,X Byte length : 2 Cycle number : 5 Timing : φ φ φ φ R ADDR DATA ...
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Instructions : ∆AND ∆$hhll ∆BIT ∆$hhll ∆CMP ∆$hhll ∆CPX ∆$hhll ∆CPY ∆$hhll ∆EOR ∆$hhll ∆LDA ∆$hhll ∆LDX ∆$hhll ∆LDY ∆$hhll ∆ORA ∆$hhll ∆SBC ∆$hhll Byte length : 3 Cycle number : 4 Timing : φ φ φ ...
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Instructions : ∆DEC ∆$hhll ∆INC ∆$hhll ∆LSR ∆$hhll ∆ROL ∆$hhll ∆ROR∆$hhll Byte length : 3 Cycle number : 6 Timing : φ SYNC R ADDR PC DATA ADDR PC H ADDR /DATA Rev.2.00 ...
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Instruction : Byte length : 3 Cycle number : 3 Timing : φ SYNC R ADDR DATA ADDR H ADDR L PC /DATA Rev.2.00 Nov 14, 2006 page 140 of 185 REJ09B0322-0200 ABSOLUTE ...
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Instruction : Byte length : 3 Cycle number : 6 Timing : φ SYNC R ADDR PC DATA Op-code ADDR ADDR L Op code /DATA Note: Some products are “01” or content ...
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Instructions : ∆STX∆$hhll ∆STY∆$hhll Byte length : 3 Cycle number : 5 Timing : φ SYNC R ADDR DATA ADDR H ADDR L /DATA Rev.2.00 Nov 14, 2006 page 142 of 185 REJ09B0322-0200 ABSOLUTE PC+2 PC+1 PC ...
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ABSOLUTE X, ABSOLUTE Y ∆ADC ∆$hhll Instructions : ∆AND ∆$hhll ∆CMP ∆$hhll ∆EOR ∆$hhll ∆LDA ∆$hhll ∆LDX ∆$hhll,Y ∆LDY ∆$hhll,X ∆ORA ∆$hhll ∆SBC ∆$hhll Byte ...
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Instructions : ∆DEC ∆$hhll,X ∆INC ∆$hhll,X ∆LSR ∆$hhll,X ∆ROL ∆$hhll,X ∆ROR ∆$hhll,X Byte length : 3 Cycle number : 7 Timing : φ SYNC R ADDR -code DATA ADDR ...
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ABSOLUTE X, ABSOLUTE Y ∆STA∆$hhll Instruction : Byte length : 3 Cycle number : 6 Timing : φ SYNC R ADDR PC Op -code DATA ADDR ADDR ...
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Instruction : Byte length : 3 Cycle number : 5 Timing : φ φ φ φ ...
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ZERO PAGE INDIRECT ∆JMP∆($zz) Instruction : Byte length : 2 Cycle number : 4 Timing : φ φ φ φ ...
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ZERO PAGE INDIRECT ∆JSR∆($zz) Instruction : Byte length : 2 Cycle number : 7 Timing : φ φ φ φ ...
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Instructions : ∆AND ∆($zz,X) ∆CMP ∆($zz,X) ∆EOR ∆($zz,X) ∆LDA ∆($zz,X) ∆ORA ∆($zz,X) ∆SBC ∆($zz,X) Byte length : 2 Cycle number : 6 Timing : φ SYNC R ADDR PC DATA Op-code ADDR ...
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Instruction : Byte length : 2 Cycle number : 7 Timing : φ φ φ φ SYNC PC ...
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Instructions : ∆AND ∆($zz),Y ∆CMP∆($zz),Y ∆EOR ∆($zz),Y ∆LDA ∆($zz),Y ∆ORA∆($zz),Y ∆SBC ∆($zz),Y Byte length : 2 Cycle number : 6 Timing : φ SYNC R ADDR DATA Op -code ADDR PC H ...
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Instruction : Byte length : 2 Cycle number : 7 Timing : φ SYNC R ADDR DATA Op -code ADDR ADDR ...
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Instructions : ∆BCS ∆$hhll ∆BEQ ∆$hhll ∆BMI ∆$hhll ∆BNE ∆$hhll ∆BPL ∆$hhll ∆BVC ∆$hhll ∆BVS ∆$hhll Byte length : 2 (1)With no branch Cycle number : 2 Timing : φ SYNC R ADDR DATA ADDR H ...
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Instructions : ∆BCS ∆$hhll ∆BEQ ∆$hhll ∆BMI ∆$hhll ∆BNE ∆$hhll ∆BPL ∆$hhll ∆BVC ∆$hhll ∆BVS ∆$hhll Byte length : 2 (2)With branch Cycle number : 4 Timing : φ φ φ φ R/W RD ...
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Instruction : Byte length : 2 Cycle number : 4 Timing : φ φ φ φ ADDR Op-code DATA ...
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Instruction : Byte length : 2 Cycle number : 5 Timing : φ SYNC R ADDR DATA Op -code PC ADDR H H ADDR code /DATA BA : Basic address ...
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Instructions : ∆AND∆#$nn ∆EOR∆#$nn ∆ORA∆#$nn ∆SBC∆#$nn Byte length : 2 Cycle number : 5 Timing : φ SYNC R ADDR PC DATA Op -code ADDR ADDR code ...
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Instruction : Byte length : 2 Cycle number : 3 Timing : φ SYNC R ADDR PC DATA ADDR ADDR /DATA Rev.2.00 Nov 14, 2006 page 158 of 185 REJ09B0322-0200 ...
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Instruction : Byte length : 2 Cycle number : 4 Timing : φ SYNC R ADDR DATA ADDR H ADDR L PC /DATA Rev.2.00 Nov 14, 2006 page 159 of 185 REJ09B0322-0200 IMMEDIATE (T= ...
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Instructions : ∆AND∆$zz ∆EOR∆$zz ∆ORA∆$zz ∆SBC∆$zz Byte length : 2 Cycle number : 6 Timing : φ SYNC R ADDR PC DATA Op -code ADDR ADDR /DATA ...
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Instruction : Byte length : 2 Cycle number : 4 Timing : φ SYNC R ADDR PC DATA PC ADDR H ADDR /DATA Rev.2.00 Nov 14, 2006 page 161 of 185 REJ09B0322-0200 ZERO ...
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Instruction : Byte length : 2 Cycle number : 5 Timing : φ SYNC R ADDR PC DATA Op -code ADDR ADDR /DATA code Rev.2.00 Nov 14, ...
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Instructions : ∆AND∆$zz,X ∆EOR∆$zz,X ∆ORA∆$zz,X ∆SBC∆$zz,X Byte length : 2 Cycle number : 7 Timing : φ SYNC R ADDR PC PC+1 DATA Op-code ADDR ADDR L Op ...
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Instruction : Byte length : 2 Cycle number : 5 Timing : φ SYNC R ADDR PC DATA Op-code ADDR ADDR L Op code /DATA Rev.2.00 Nov 14, 2006 page ...
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Instruction : Byte length : 2 Cycle number : 6 Timing : φ φ φ φ SYNC ADDR PC PC+1 DATA Op-code ...
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Instructions : ∆AND∆$hhll ∆EOR∆$hhll ∆ORA∆$hhll ∆SBC∆$hhll Byte length : 3 Cycle number : 7 Timing : φ φ φ φ ADDR ...
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Instruction : Byte length : 3 Cycle number : 5 Timing : φ φ φ φ ADDR PC DATA ADDR P ...
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Instruction : Byte length : 3 Cycle number : 6 Timing : φ φ φ φ ADDR Op-code ADDR P C ...
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ABSOLUTE X, ABSOLUTE Y ∆ADC∆$hhll Instructions : ∆AND∆$hhll ∆EOR∆$hhll ∆ORA∆$hhll ∆SBC∆$hhll Byte length : 3 Cycle number : 8 Timing : φ SYNC R ADDR PC PC ...
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ABSOLUTE X, ABSOLUTE Y ∆CMP∆$hhll (T=1) Instruction : Byte length : 3 Cycle number : 6 Timing : φ SYNC R ADDR DATA Op -code PC ADDR H H ADDR L O ...
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ABSOLUTE X, ABSOLUTE Y ∆LDA∆$hhll (T=1) Instruction : Byte length : 3 Cycle number : 7 Timing : φ SYNC R ADDR DATA Op -code ADDR ADDR L ...
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Instructions : ∆AND∆($zz,X) ∆EOR∆($zz,X) ∆ORA∆($zz,X) ∆SBC∆($zz,X) Byte length : 2 Cycle number : 9 Timing : φ φ φ φ R ADDR PC PC+1 Op- DATA B A code A D ...
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Instruction : Byte length : 2 Cycle number : 7 Timing : φ φ φ φ PC ...
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Instruction : Byte length : 2 Cycle number : 8 Timing : φ φ φ φ ADDR PC PC DATA ADDR ...
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Instructions : ∆AND∆($zz),Y ∆EOR∆($zz),Y ∆ORA∆($zz),Y ∆SBC∆($zz),Y 2 Byte length : 9 Cycle number : Timing : φ φ φ φ ...
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Instruction : Byte length : 2 Cycle number : 7 Timing : φ φ φ φ ADDR DATA Op-code ...
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Instruction : Byte length : 2 Cycle number : 8 Timing : φ φ φ φ PC+1 Op ...
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APPENDIX 2 APPENDIX 2. 740 Family Machine Language Instruction Table Parameter SYMBOL Classification LDA # $ nn (A)←nn LDA $ zz (A)←(M) LDA $ zz, X (A)←(M) LDA $ hhII (A)←(M) LDA $ hhII, X (A)←(M) LDA $ hhII, Y ...
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Parameter SYMBOL Classification (A)←(A)+nn+(C) ADC # $ nn (A)←(A)+(M)+(C) ADC $ zz (A)←(A)+(M)+(C) ADC $ zz, X (A)←(A)+(M)+(C) ADC $ hhII ADC $ hhII, X (A)←(A)+(M)+(C) ADC $ hhII, Y (A)←(A)+(M)+(C) ADC ($ zz, X) (A)←(A)+(M)+(C) (A)←(A)+(M)+(C) ADC ($ zz), ...
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Parameter SYMBOL Classification AND # $ nn (A)←(A) nn (A)←(A) (M) AND $ zz (A)←(A) (M) AND $ zz, X (A)←(A) (M) AND $ hhII (A)←(A) (M) AND $ hhII, X (A)←(A) (M) AND $ hhII, Y (A)←(A) (M) AND ...
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Parameter SYMBOL Classification Left Shift C ←A ASL A ASL $ zz ASL $ zz, X Left Shift C ← M ASL $ hhII ASL $ hhII, X Right Shift 0 → ...
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Parameter SYMBOL Classification (PC) ← (PC)+2+Rel BRA $ hhII (PC) ← hhII JMP $ hhII ) ← (hhII), (PC (PC JMP ($ hhII ←(zz), (PC (PC JMP ($ zz) L (M(S))←(PC H JSR $ hhII (S)←(S) –1, and ...
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Symbol Means A Accumulator Ai Bit i of accumulator X Index register X Y Index register Y M Memory Mi Bit i of memory PS Processor status register S Stack Pointer PC Program counter PC Low-order byte of program counter ...
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APPENDIX 3 APPENDIX 3. 740 Family Iist of Instruction Codes D – D 0000 0001 3 0 Hexadecimal – notation ORA BRK 0000 0 IND, X ZP, IND ORA BPL 0001 1 IND, Y ...
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MEMORANDUM Rev.2.00 Nov 14, 2006 page 185 of 185 REJ09B0322-0200 740 Family Iist of Instruction Codes ...
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Family Software Manual Publication Data : Rev.1.00 Aug 29, 1997 Rev.2.00 Nov 14, 2006 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2006. Renesas Technology Corp., All rights reserved. Printed in Japan. ...
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Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan 740 Family Software Manual REJ09B0322-0200 ...