HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 780

MPU 3V 16K PB-FREE 208-QFP

HD6417750SF200V

Manufacturer Part Number
HD6417750SF200V
Description
MPU 3V 16K PB-FREE 208-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750SF200V

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 2.07 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750SF200V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 15 Serial Communication Interface (SCI)
Rev.7.00 Oct. 10, 2008 Page 694 of 1074
REJ09B0366-0700
No
No
Read ORER, PER, and FER flags
Read receive data in SCRDR1,
Read RDRF flag in SCSSR1
Clear RE bit in SCSCR1 to 0
and clear RDRF flag
All data received?
Start of reception
End of reception
in SCSSR1 to 0
or ORER = 1?
PER or FER
Figure 15.10 Sample Serial Reception Flowchart (1)
in SCSSR1
RDRF = 1?
Yes
Yes
No
Error handling
Yes
1. Receive error handling and
2. SCI status check and receive
3. Serial reception continuation
break detection: If a receive
error occurs, read the ORER,
PER, and FER flags in
SCSSR1 to identify the error.
After performing the
appropriate error handling,
ensure that the ORER, PER,
and FER flags are all cleared to
0. Reception cannot be
resumed if any of these flags
are set to 1. In the case of a
framing error, a break can be
detected by reading the value
of the RxD pin.
data read : Read SCSSR1 and
check that RDRF = 1, then read
the receive data in SCRDR1
and clear the RDRF flag to 0.
procedure: To continue serial
reception, complete zero-
clearing of the RDRF flag
before the stop bit for the
current frame is received. (The
RDRF flag is cleared
automatically when the direct
memory access controller
(DMAC) is activated by an RXI
interrupt and the SCRDR1
value is read.)

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