HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 216

• Manufacturer Part Number: HD6417750SF200V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF200V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 4 Caches
• Data array
• LRU (SH7750R only)
4.4.2
When the IC is enabled (CCR.ICE = 1) and instruction fetches are performed by means of an
effective address from a cacheable area, the instruction cache operates as follows:
1. The tag and V bit are read from the cache line indexed by effective address bits [12:5].
2. The tag is compared with bits [28:10] of the address resulting from effective address
3a. Cache hit
3b. Cache miss
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REJ09B0366-0700
The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized
by a power-on or manual reset.
In a 2-way set-associative cache, up to 2 items of data can be registered in the cache at each
entry address. When an entry is registered, the LRU bit indicates which of the 2 ways it is to be
registered in. The LRU bit is a single bit of each entry, and its usage is controlled by hardware.
The LRU (least-recently-used) algorithm is used for way selection, and selects the less recently
accessed way. The LRU bits are initialized to 0 by a power-on reset but not by a manual reset.
The LRU bits cannot be read or written by software.
translation by the MMU:
•
•
•
•
The data indexed by effective address bits [4:2] is read as an instruction from the data field of
the cache line indexed by effective address bits [12:5].
Data is read into the cache line from the external memory space corresponding to the effective
address. Data reading is performed, using the wraparound method, in order from the longword
data corresponding to the effective address, and when the corresponding data arrives in the
cache, the read data is returned to the CPU as an instruction. When reading of one line of data
is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is
written to the V bit.
If the tag matches and the V bit is 1
If the tag matches and the V bit is 0
If the tag does not match and the V bit is 0
If the tag does not match and the V bit is 1
Read Operation
→ (3a)
→ (3b)
→ (3b)
→ (3b)