HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 31

MPU 3V 16K PB-FREE 208-QFP

HD6417750SF200V

Manufacturer Part Number
HD6417750SF200V
Description
MPU 3V 16K PB-FREE 208-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750SF200V

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 2.07 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750SF200V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Item
19.4.1 Interrupt
Operation Sequence
Figure 19.3 Interrupt
Operation Flowchart
19.6 Usage Notes
Page
843
844
847 to
849
Revision (See Manual for Details)
Description and notes amended
3. The priority level of the interrupt selected by the interrupt
...
Notes: 1. The interrupt mask bits (IMASK) in the status register
Figure amended
Newly added
Note: * IMASK: Interrupt mask bits in status register (SR)
controller is compared with the interrupt mask bits (IMASK) in
the status register (SR) of the CPU. If the request priority
level is higher that the level in bits IMASK, the interrupt
controller accepts the interrupt and sends an interrupt
request signal to the CPU.
Set BL, MD, RB bits
Branch to exception
Set interrupt source
Save SR to SSR;
save PC to SPC
2. The interrupt source flag should be cleared in the
in INTEVT
in SR to 1
handler
(SR) are not changed by acceptance of an interrupt in
this LSI.
interrupt handler. To ensure that an interrupt request
that should have been cleared is not inadvertently
accepted again, read the interrupt source flag after it
has been cleared, then wait for the interval shown in
table 19.9 (Time for priority decision and SR mask bit
comparison) before clearing the BL bit or executing
an RTE instruction.
Yes
interrupt?
IMASK * =
level 14 or
Rev.7.00 Oct. 10, 2008 Page xxix of lxxxiv
Level 15
lower?
Yes
No
Yes
No
interrupt?
level 13 or
Level 14
IMASK =
lower?
Yes
No
Yes
No
interrupt?
IMASK =
level 0?
REJ09B0366-0700
Level 1
Yes
No
No

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