HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 581

Manufacturer Part Number

HD6417750SF200V

MPU 3V 16K PB-FREE 208-QFP

Manufacturer

Renesas Electronics America

SuperH® SH7750r

Core Processor

Connectivity

EBI/EMI, FIFO, SCI, SmartCard

DMA, POR, WDT

Number Of I /o

Program Memory Type

Voltage - Supply (vcc/vdd)

1.8 V ~ 2.07 V

Oscillator Type

Operating Temperature

-20°C ~ 75°C

Package / Case

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Program Memory Size

Data Converters

Manufacturer

BOSTOCK HK LIMITED

Part Number:

HD6417750SF200V

Manufacturer:

Renesas Electronics America

• When setting the mode register of the synchronous DRAM, set the address for area 2.

• Control signals required in this connection are RAS, CAS, RD/WR, CS3, DQM0−DQM7, and

• Do not use partial-sharing mode. If you use this, correct operation is not guaranteed.

Figure 13.45 Example of the Connection of Synchronous DRAM with 64-bit Bus Width

cycles. The interval cycle number between the second REF command and the next ACTV

command issuance is specified by the settings of both the TRAS2–TRAS0 bits and the TRC2–

TRC0 bits in MCR in the sum total, which is 4 to 32 CKIO cycles. Set RTCOR and bits

CKS2–CKS0, and MCR so as to satisfy the refresh-interval rating of the synchronous DRAM

which you are using. The synchronous DRAM auto-refresh timing with 64-bit bus width is

shown below figure.

CKE. CS2 is not used.

Rev.7.00 Oct. 10, 2008 Page 495 of 1074

Section 13 Bus State Controller (BSC)

REJ09B0366-0700