HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 165

MPU 3V 16K PB-FREE 208-QFP

HD6417750SF200V

Manufacturer Part Number
HD6417750SF200V
Description
MPU 3V 16K PB-FREE 208-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750SF200V

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 2.07 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750SF200V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
3.3
3.3.1
The SH-4 supports a 32-bit physical address space, and can access a 4-Gbyte address space. When
the MMUCR.AT bit is cleared to 0 and the MMU is disabled, the address space is this physical
address space. The physical address space is divided into a number of areas, as shown in figure
3.3. The physical address space is permanently mapped onto 29-bit external memory space; this
correspondence can be implemented by ignoring the upper 3 bits of the physical address space
addresses. In privileged mode, the 4-Gbyte space from the P0 area to the P4 area can be accessed.
In user mode, a 2-Gbyte space in the U0 area can be accessed. Accessing the P1 to P4 areas
(except the store queue area) in user mode will cause an address error.
H'0000 0000
H'8000 0000
H'A000 0000
H'C000 0000
H'E000 0000
H'FFFF FFFF
MMU exceptions are not generated when the AT bit is 0. In the case of software that does not
use the MMU, therefore, the AT bit should be cleared to 0.
Address Space
Physical Address Space
Privileged mode
Non-cacheable
Non-cacheable
Figure 3.3 Physical Address Space (MMUCR.AT = 0)
Cacheable
Cacheable
Cacheable
P0 area
P1 area
P2 area
P3 area
P4 area
memory space
External
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
Section 3 Memory Management Unit (MMU)
Rev.7.00 Oct. 10, 2008 Page 79 of 1074
Store queue area
Address error
Address error
User mode
Cacheable
U0 area
REJ09B0366-0700
H'0000 0000
H'8000 0000
H'E000 0000
H'E400 0000
H'FFFF FFFF

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