HD6417750SF200V Renesas Electronics America, HD6417750SF200V Datasheet - Page 428

• Manufacturer Part Number: HD6417750SF200V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF200V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 12 Timer Unit (TMU)
12.2.2
TSTR is an 8-bit readable/writable register that specifies whether the channel 0–2 timer counters
(TCNT) are operated or stopped.
TSTR is initialized to H'00 by a power-on or manual reset, or standby mode. In module standby
mode, TSTR is not initialized when the input clock selected by each channel is the on-chip RTC
output clock (RTCCLK), and is initialized only when the input clock is the external clock (TCLK)
or internal clock (Pck).
Bits 7 to 3—Reserved: These bits are always read as 0. A write to these bits is invalid, but the
write value should always be 0.
Bit 2—Counter Start 2 (STR2): Specifies whether timer counter 2 (TCNT2) is operated or
stopped.
Bit 2: STR2
0
1
Bit 1—Counter Start 1 (STR1): Specifies whether timer counter 1 (TCNT1) is operated or
stopped.
Bit 1: STR1
0
1
Rev.7.00 Oct. 10, 2008 Page 342 of 1074
REJ09B0366-0700
Initial value:
Timer Start Register (TSTR)
R/W:
Bit:
Description
TCNT2 count operation is stopped
TCNT2 performs count operation
Description
TCNT1 count operation is stopped
TCNT1 performs count operation
—
R
7
0
—
R
6
0
—
R
5
0
—
R
4
0
—
R
3
0
STR2
R/W
2
0
STR1
R/W
1
0
(Initial value)
(Initial value)
STR0
R/W
0
0