HD6417750SF167V Renesas Electronics America, HD6417750SF167V Datasheet - Page 933

• Manufacturer Part Number: HD6417750SF167V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF167V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 167MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19.6
19.6.1
When multiple NMI interrupts are input to the NMI pin within a set period of time (which is
dependent on the internal state of the CPU and the external bus state), subsequent interrupts may
not be accepted.
Note that this problem does not occur when sufficient time*
inputs or with non-NMI interrupts such as IRL interrupts.
Workarounds: Methods 1, 2, or 3 below may be used to avoid the above problem.
1. Allow sufficient time between NMI interrupt inputs, as described in note 1, below.
2. Do not use NMI interrupts. Use IRL interrupts instead.
3. Workaround using software
Notes: 1. If SR.BL is cleared to 0 so that one or more instructions may be executed between the
Note that it may not be possible to assure the above interval between NMI interrupt inputs if
hazard is input to NMI, and that this may cause the device to malfunction. Design the external
circuits so that no hazard is input via NMI.*
The above problem can be avoided by inserting the following lines of code*
exception handling routine.
2. When changing the level of the NMI input, ensure that the high and low durations are
3. If the NMI exception handling routine contains code that changes the value of the
4. Registers R0 to R3 in the code sample can be changed to any general register. Also, the
Usage Notes
NMI Interrupts (SH7750 and SH7750S Only)
handling of two NMI interrupts.
at least 5 CKIO cycles. Also ensure that no noise pulses occur before or after level
changes.
SR.BL bit, the code listed below should be inserted before the point at which the
change is made.
necessary register save and restore instructions should be inserted before and after the
code listed below, as appropriate.
2
Rev.7.00 Oct. 10, 2008 Page 847 of 1074
1
Section 19 Interrupt Controller (INTC)
is provided between NMI interrupt
3
REJ09B0366-0700
*
4
into the NMI