HD6417750SF167V Renesas Electronics America, HD6417750SF167V Datasheet - Page 645

• Manufacturer Part Number: HD6417750SF167V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF167V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 167MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit 16—Acknowledge Level (AL): Specifies the DACK (acknowledge) signal as active-high or
active-low.
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, this bit is
invalid.
Bit 16: AL
0
1
Bits 15 and 14—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify
incrementing/decrementing of the DMA transfer destination address. The specification of these
bits is ignored when data is transferred from external memory to an external device in single
address mode. For channel 0, in DDT mode these bits are set to DM1 = 0 and DM0 = 1 with the
DTR format.
Bit 15: DM1
0
1
Bit 14: DM0
0
1
0
1
Description
Active-high output
Active-low output
Description
Destination address fixed
Destination address incremented (+1 in 8-bit transfer, +2 in 16-
bit transfer, +4 in 32-bit transfer, +8 in 64-bit transfer, +32 in 32-
byte burst transfer)
Destination address decremented (–1 in 8-bit transfer, –2 in 16-
bit transfer, –4 in 32-bit transfer, –8 in 64-bit transfer, –32 in 32-
byte burst transfer)
Setting prohibited
Section 14 Direct Memory Access Controller (DMAC)
Rev.7.00 Oct. 10, 2008 Page 559 of 1074
REJ09B0366-0700
(Initial value)
(Initial value)