HD6417750SF167V Renesas Electronics America, HD6417750SF167V Datasheet - Page 929

• Manufacturer Part Number: HD6417750SF167V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF167V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 167MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19.4
19.4.1
The sequence of operations when an interrupt is generated is described below. Figure 19.3 shows a
flowchart of the operations.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent,
3. The priority level of the interrupt selected by the interrupt controller is compared with the
4. The CPU accepts an interrupt at a break between instructions.
5. The interrupt source code is set in the interrupt event register (INTEVT).
6. The status register (SR) and program counter (PC) are saved to SSR and SPC, respectively.
7. The block bit (BL), mode bit (MD), and register bank bit (RB) in SR are set to 1.
8. The CPU jumps to the start address of the interrupt handler (the sum of the value set in the
The interrupt handler may branch with the INTEVT register value as its offset in order to identify
the interrupt source. This enables it to branch to the handling routine for the particular interrupt
source.
Notes: 1. The interrupt mask bits (IMASK) in the status register (SR) are not changed by
according to the priority levels set in interrupt priority registers A to C (IPRA–IPRC). Lower-
priority interrupts are held pending. If two of these interrupts have the same priority level, or if
multiple interrupts occur within a single module, the interrupt with the highest priority
according to table 19.5, Interrupt Exception Handling Sources and Priority Order, is selected.
interrupt mask bits (IMASK) in the status register (SR) of the CPU. If the request priority level
is higher that the level in bits IMASK, the interrupt controller accepts the interrupt and sends
an interrupt request signal to the CPU.
The R15 contents at this time are saved in SGR.
vector base register (VBR) and H'00000600).
2. The interrupt source flag should be cleared in the interrupt handler. To ensure that an
3. For some interrupt sources, their interrupt masks (INTMSK00) must e cleared using
INTC Operation
Interrupt Operation Sequence
acceptance of an interrupt in this LSI.
interrupt request that should have been cleared is not inadvertently accepted again, read
the interrupt source flag after it has been cleared, then wait for the interval shown in
table 19.9 (Time for priority decision and SR mask bit comparison) before clearing the
BL bit or executing an RTE instruction.
the INTMSKCLR00 register.
Rev.7.00 Oct. 10, 2008 Page 843 of 1074
Section 19 Interrupt Controller (INTC)
REJ09B0366-0700