HD6417750SF167V Renesas Electronics America, HD6417750SF167V Datasheet - Page 451

• Manufacturer Part Number: HD6417750SF167V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF167V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 167MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13.1.5
Space Divisions: The architecture of this LSI provides a 32-bit virtual address space. The virtual
address is divided into five areas according to the upper address value. External memory space
comprises a 29-bit address space, divided into eight areas.
The virtual address can be allocated to any external address by means of the memory management
unit (MMU). Details are given in section 3, Memory Management Unit (MMU). This section
describes the areas into which the external address is divided.
With this LSI, various kinds of memory or PC cards can be connected to the seven areas of
external address as shown in table 13.3, and chip select signals (CS0–CS6, CE2A, CE2B) are
output for each of these areas. CS0 is asserted when accessing area 0, and CS6 when accessing
area 6. When DRAM or synchronous DRAM is connected to area 2 or 3, signals such as RAS,
CAS, RD/WR, and DQM are also asserted. When the PCMCIA interface is selected for area 5 or
6, CE2A, CE2B is asserted in addition to CS5, CS6 for the byte to be accessed.
Figure 13.2 Correspondence between Virtual Address Space and External Memory Space
H'0000 0000
H'8000 0000
H'A000 0000
H'C000 0000
H'E000 0000
H'E400 0000
H'FFFF FFFF
Notes: 1. When the MMU is off (MMUCR.AT = 0), the top 3 bits of the 32-bit address are ignored, and
Overview of Areas
2. When the MMU is on (MMUCR.AT = 1), the P0, U0, P3, and store queue areas can be
memory is mapped onto a fixed 29-bit external address.
mapped onto any external address using the TLB.
For details, see section 3, Memory Management Unit (MMU).
Physical address
Store queue area
(MMU off)
U0 areas
P1 area
P2 area
P3 area
P4 area
P0 and
space
256
Virtual address
Store queue area
(MMU on)
U0 areas
P1 area
P2 area
P3 area
P4 area
P0 and
space
Rev.7.00 Oct. 10, 2008 Page 365 of 1074
Section 13 Bus State Controller (BSC)
Area 7 (reserved area)
External memory
Area 0 (CS0)
Area 1 (CS1)
Area 2 (CS2)
Area 3 (CS3)
Area 4 (CS4)
Area 5 (CS5)
Area 6 (CS6)
space
REJ09B0366-0700
H'0000 0000
H'0400 0000
H'0800 0000
H'0C00 0000
H'1000 0000
H'1400 0000
H'1800 0000
H'1C00 0000
H'1FFF FFFF