HD6417750SF167V Renesas Electronics America, HD6417750SF167V Datasheet - Page 578

• Manufacturer Part Number: HD6417750SF167V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF167V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 167MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Bus State Controller (BSC)
• Burst Read
Rev.7.00 Oct. 10, 2008 Page 492 of 1074
REJ09B0366-0700
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
D31–D0 (read)
BS
CKE
DACKn
(SA: IO ← memory)
Figure 13.43 is the timing chart of a burst-read operation with a burst length of 4. Following
the Tr cycle, during which an ACTV command is output, a READ command is issued during
cycle Tc1, and a READA command is issued four cycles later. During the Td1 to Td8 cycles,
read data are accepted on the rising edges of the external command clock (CKIO). Tpc is the
cycle used to wait for the auto-precharging, which is triggered by the READA command, to be
completed in the synchronous DRAM. During this cycle, a new command for accessing the
same bank cannot be issued. In the SH7750R, the number of Tpc cycles is determined by the
setting of the TPC2 to TPC0 bits of MCR, and no command that operates on the synchronous
DRAM may be issued during these cycles.
Figure 13.43 Basic Timing of Synchronous DRAM Burst Read (Burst Length = 4)
Tr
Row
Row
Row
Trw
Tc1
c1
H/L
Tc2
Tc3
Tc4/Td1
c1
Td2
H/L
c5
c2
Td3
c3
Td4
c4
Td5
c5
Td6
c6
Td7
c7
Td8
c8
Tpc