HD6417750SF167V Renesas Electronics America, HD6417750SF167V Datasheet - Page 206

• Manufacturer Part Number: HD6417750SF167V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF167V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 167MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 4 Caches
4.3.2
When the OC is enabled (CCR.OCE = 1) and data is read by means of an effective address from a
cacheable area, the cache operates as follows:
1. The tag, V bit, and U bit are read from the cache line indexed by effective address bits [13:5].
2. The tag is compared with bits [28:10] of the address resulting from effective address
3a. Cache hit
3b. Cache miss (no write-back)
3c. Cache miss (with write-back)
Rev.7.00 Oct. 10, 2008 Page 120 of 1074
REJ09B0366-0700
translation by the MMU:
The data indexed by effective address bits [4:0] is read from the data field of the cache line
indexed by effective address bits [13:5] in accordance with the access size
(quadword/longword/word/byte).
Data is read into the cache line from the external memory space corresponding to the effective
address. Data reading is performed, using the wraparound method, in order from the longword
data corresponding to the effective address, and when the corresponding data arrives in the
cache, the read data is returned to the CPU. While the remaining one cache line of data is being
read, the CPU can execute the next processing. When reading of one line of data is completed,
the tag corresponding to the effective address is recorded in the cache, and 1 is written to the V
bit.
The tag and data field of the cache line indexed by effective address bits [13:5] are saved in the
write-back buffer. Then data is read into the cache line from the external memory space
corresponding to the effective address. Data reading is performed, using the wraparound
method, in order from the longword data corresponding to the effective address, and when the
corresponding data arrives in the cache, the read data is returned to the CPU. While the
remaining one cache line of data is being read, the CPU can execute the next processing. When
reading of one line of data is completed, the tag corresponding to the effective address is
recorded in the cache, 1 is written to the V bit, and 0 to the U bit. The data in the write-back
buffer is then written back to external memory.
• If the tag matches and the V bit is 1
• If the tag matches and the V bit is 0
• If the tag does not match and the V bit is 0
• If the tag does not match, the V bit is 1, and the U bit is 0 → (3b)
• If the tag does not match, the V bit is 1, and the U bit is 1 → (3c)
Read Operation
→ (3a)
→ (3b)
→ (3b)