HD6417727F160CV Renesas Electronics America, HD6417727F160CV Datasheet - Page 975

IC SH MPU ROMLESS 240QFN

HD6417727F160CV

Manufacturer Part Number
HD6417727F160CV
Description
IC SH MPU ROMLESS 240QFN
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727F160CV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
160MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.7 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Table 31.1 shows H-UDI register configuration.
Table 31.1 H-UDI Registers
Name
Instruction register
Device Identification
register
Boundary-scan
register
Note: * Initialized when TRST pin is low or when TAP is in the test-logic-reset state.
31.3.1
The bypass register (SDBPR) is a 1-bit register that cannot be accessed by the CPU. Setting the
SDIR register to the bypass mode makes the SDBPR register to be connected between the TDI
and TDO H-UDI pins.
31.3.2
The instruction register (SDIR) is a 16-bit read-only register. The register is in bypass mode in its
initial state. It is initialized by TRST or in the TAP test-logic-reset state, and can be written by the
H-UDI irrespective of the CPU mode. Operation is not guaranteed when a reserved command is
set to this register.
Bits 15 to 12—Test Instruction Bits (TI3 to TI0): Cannot be written by the CPU.
Initial value:
Initial value:
Bypass Register (SDBPR)
Instruction Register (SDIR)
Bit:
Bit:
Abbreviation R/W
SDIR
SDID
SDBSR
TI3
15
1
7
1
TI2
14
1
6
1
R
TI1
13
1
5
1
Size
16
CPU Side
Section 31 User-Debugging Interface (H-UDI)
TI0
12
1
4
1
Address
H’04000200
Rev.6.00 Mar. 27, 2009 Page 917 of 1036
11
1
3
1
R/W
R/W
R
R/W
H-UDI Side
10
1
2
1
Size
16
32
REJ09B0254-0600
9
1
1
1
Initial
Value*
H’FFFF
H’0004200F
Undefined
8
1
0
1

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