HD6417727F160CV Renesas Electronics America, HD6417727F160CV Datasheet - Page 752

• Manufacturer Part Number: HD6417727F160CV
• Description: IC SH MPU ROMLESS 240QFN
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 23 USB Function Controller
Name
Interrupt select register 0
Interrupt select register 1
Note: * If the MMU does not convert addresses, use addresses in parentheses.
23.5
23.5.1
USBEPDR0I is an 8-byte FIFO buffer for endpoint 0, holding one packet of transmit data for
control-in. Transmit data is fixed by writing one packet of data and setting bit 0 in the USB trigger
register. When an ACK handshake is returned from the host after the data has been transmitted,
EP0i TS in USB interrupt flag register 0 is set. This FIFO buffer can be initialized by means of
EP0i CLR in the USBFIFO clear register.
23.5.2
USBEPDR0O is an 8-byte receive FIFO buffer for endpoint 0. USBEPDR0O holds endpoint 0
receive data other than setup commands. When data is received normally, EP0o TS in USB
interrupt flag register 0 is set, and the number of receive bytes is indicated in the EP0o receive
data size register. After the data has been read, setting EP0o RDFN in the USB trigger register
enables the next packet to be received. This FIFO buffer can be initialized by means of EP0o CLR
in the USBFIFO clear register.
23.5.3
USBEPDR0S is an 8-byte FIFO buffer specifically for endpoint 0 setup command reception.
USBEPDR0S receives only setup commands requiring processing on the application side. When
command data is received normally, SETUP TS in USB interrupt flag register 0 is set. As a setup
command must be received without fail, if data is left in this buffer, it will be overwritten with
new data. If reception of the next command is started while the current command is being read,
command reception has priority, the read by the application is forcibly terminated, and the read
data is invalid.
Rev.6.00 Mar. 27, 2009 Page 694 of 1036
REJ09B0254-0600
Register Descriptions
USBEP0i Data Register (USBEPDR0I)
USBEP0o Data Register (USBEPDR0O)
USBEP0s Data Register (USBEPDR0S)
Abbreviation
USBISR0
USBISR1
R/W
R/W
R/W
H'00
H'07
Initial Value
Address
H'0400024A
(H'A400024A)*
H'04000250
(H'A4000250)*
Access Size
8
8