HD6417727F160CV Renesas Electronics America, HD6417727F160CV Datasheet - Page 214

• Manufacturer Part Number: HD6417727F160CV
• Description: IC SH MPU ROMLESS 240QFN
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 5 Cache
5.3.2
Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. The
LRU is updated.
Read Miss: An external bus cycle starts and the entry is updated. The way replaced is the one
least recently used. Entries are updated in 16-byte units. When the desired instruction or data that
caused the miss is loaded from external memory to the cache, the instruction or data is transferred
to the CPU in parallel with being loaded to the cache. When it is loaded in the cache, the U bit is
cleared to 0 and the V bit is set to 1. In the write-back mode, when the U bit of the entry to be
replaced is 1, the cache update cycle starts after the entry is transferred to the write-back buffer.
After the cache completes its update cycle, the write-back buffer writes back the entry to the
memory. The write-back unit is 16 bytes.
5.3.3
Prefetch Hit: The LRU is updated so that the hit way becomes the most recent. Other cache
contents are not updated. Instruction or data transfer to the CPU is not performed.
Prefetch Miss: Instruction or data transfer to the CPU is not performed, and the way replaced is as
shown in table 5.2, table 5.4, table 5.5, and table 5.6. Other operations are the same as in the case
of a read miss.
5.3.4
Write Hit: In a write access in the write-back mode, the data is written to the cache and the U bit
of the entry written is set to 1. Writing occurs only to the cache; no external memory write cycle is
issued. In the write-through mode, the data is written to the cache and an external memory write
cycle is issued.
Write Miss: In the write-back mode, an external write cycle starts when a write miss occurs, and
the entry is updated. The way to be replaced is the one least recently used. When the U bit of the
entry to be replaced is 1, the cache update cycle starts after the entry is transferred to the write-
back buffer. The write-back unit is 16 bytes. Data is written to the cache and the U bit is set to 1
and the V bit is also set to 1. After the cache completes its update cycle, the write-back buffer
writes back the entry to the memory. In the write-through mode, no write to cache occurs in a
write miss; the write is only to the external memory.
Rev.6.00 Mar. 27, 2009 Page 156 of 1036
REJ09B0254-0600
Read Access
Write Access
Prefetch Operations