HD6417727F160CV Renesas Electronics America, HD6417727F160CV Datasheet - Page 548

• Manufacturer Part Number: HD6417727F160CV
• Description: IC SH MPU ROMLESS 240QFN
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 17 Serial Communication Interface (SCI)
Bit 5: PE
0
1
Note: * When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the
Bit 4—Parity Mode (O/E): Selects even or odd parity when parity bits are added and checked.
The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set
to 1 to enable parity addition and check. The O/E setting is ignored in the clock synchronous
mode, or in the asynchronous mode when parity addition and check is disabled.
Bit 4: O/E
0
1
Notes: 1. If even parity is selected, the parity bit is added to transmit data to make an even
Bit 3—Stop Bit Length (STOP): Selects one or two bits as the stop bit length in the
asynchronous mode. This setting is used only in the asynchronous mode. It is ignored in the clock
synchronous mode because no stop bits are added.
In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of
the next incoming character.
Bit 3: STOP
0
1
Notes: 1. In transmitting, a single bit of 1 is added at the end of each transmitted character.
Rev.6.00 Mar. 27, 2009 Page 490 of 1036
REJ09B0254-0600
2. If odd parity is selected, the parity bit is added to transmit data to make an odd number
2. In transmitting, two bits of 1 are added at the end of each transmitted character.
parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E)
mode setting.
number of 1s in the transmitted character and parity bit combined. Receive data is
checked to see if it has an even number of 1s in the received character and parity bit
combined.
of 1s in the transmitted character and parity bit combined. Receive data is checked to
see if it has an odd number of 1s in the received character and parity bit combined.
Description
Parity bit not added or checked
Parity bit added and checked*
Description
Even parity *
Odd parity *
Description
One stop bit *
Two stop bits *
2
1
1
2
(Initial value)
(Initial value)
(Initial value)