DF2378RVFQ34WV Renesas Electronics America, DF2378RVFQ34WV Datasheet - Page 769

• Manufacturer Part Number: DF2378RVFQ34WV
• Description: MCU 3V 512K I-TEMP PB-FREE 144-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378RVFQ34WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 34MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Smart Card Interface Mode (When SMIF in SCMR is 1)
Bit
7
6
5
4
3
Bit Name
TIE
RIE
TE
RE
MPIE
Initial Value
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Section 15 Serial Communication Interface (SCI, IrDA)
Description
Transmit Interrupt Enable
When this bit is set to 1, TXI interrupt request is
enabled. TXI interrupt request cancellation can be
performed by reading 1 from the TDRE flag, then
clearing it to 0, or clearing the TIE bit to 0.
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
RXI and ERI interrupt request cancellation can be
performed by reading 1 from the RDRF flag, or the
FER, PER, or ORER flag, then clearing the flag to
0, or by clearing the RIE bit to 0.
Transmit Enable
When this bit is set to 1, transmission is enabled. In
this state, serial transmission is started when
transmit data is written to TDR and the TDRE flag
in SSR is cleared to 0. SMR setting must be
performed to decide the transfer format before
setting the TE bit to 1.
The TDRE flag in SSR is fixed at 1 if transmission
is disabled by clearing this bit to 0.
Receive Enable
When this bit is set to 1, reception is enabled.
Serial reception is started in this state when a start
bit is detected in asynchronous mode or serial
clock input is detected in clocked synchronous
mode. SMR setting must be performed to decide
the transfer format before setting the RE bit to 1.
Clearing the RE bit to 0 does not affect the RDRF,
FER, PER, and ORER flags, which retain their
states.
Multiprocessor Interrupt Enable (enabled only when
the MP bit in SMR is 1 in asynchronous mode)
Write 0 to this bit in Smart Card interface mode.
Rev.7.00 Mar. 18, 2009 page 701 of 1136
REJ09B0109-0700