DF2378RVFQ34WV Renesas Electronics America, DF2378RVFQ34WV Datasheet - Page 303

• Manufacturer Part Number: DF2378RVFQ34WV
• Description: MCU 3V 512K I-TEMP PB-FREE 144-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378RVFQ34WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 34MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Set a value in RTCOR and bits RTCK2 to RTCK0 that will meet the refreshing interval
specification for the synchronous DRAM used.
When bits RTCK2 to RTCK0 are set, RTCNT starts counting up. RTCNT and RTCOR settings
should therefore be completed before setting bits RTCK2 to RTCK0. Auto refresh timing is shown
in figure 6.54.
Since the refresh counter operation is the same as the operation in the DRAM interface, see
section 6.6.12, Refresh Control.
When the continuous synchronous DRAM space is set, access to external address space other than
continuous synchronous DRAM space cannot be performed in parallel during the auto refresh
period, since the setting of the CBRM bit of REFCR is ignored.
When the interval specification from the PALL command to the REF command cannot be
satisfied, setting the RCW1 and RCW0 bits of REFCR enables one to three wait states to be
inserted after the T
number of waits according to the synchronous DRAM connected and the operating frequency of
this LSI. Figure 6.55 shows the timing when one wait state is inserted. Since the setting of bits
Address bus
Precharge-sel
SDRAMφ
CKE
Rp
RAS
CAS
WE
φ
cycle that is set by the TPC1 and TPC0 bits of DRACCR. Set the optimum
PALL
Figure 6.54 Auto Refresh Timing
T Rp
REF
T Rr
High
Rev.7.00 Mar. 18, 2009 page 235 of 1136
T Rc1
NOP
Section 6 Bus Controller (BSC)
T Rc2
REJ09B0109-0700