DF2378RVFQ34WV Renesas Electronics America, DF2378RVFQ34WV Datasheet - Page 664

• Manufacturer Part Number: DF2378RVFQ34WV
• Description: MCU 3V 512K I-TEMP PB-FREE 144-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378RVFQ34WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 34MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 16-Bit Timer Pulse Unit (TPU)
11.4.4
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 (channel 4) counter clock at overflow/underflow of
TCNT_2 (TCNT_5) as set in bits TPSC2 to TPSC0 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 11.29 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid
Table 11.29 Cascaded Combinations
Combination
Channels 1 and 2
Channels 4 and 5
Example of Cascaded Operation Setting Procedure: Figure 11.17 shows an example of the
setting procedure for cascaded operation.
Rev.7.00 Mar. 18, 2009 page 596 of 1136
REJ09B0109-0700
and the counter operates independently in phase counting mode.
Cascaded Operation
<Cascaded operation>
Cascaded operation
Figure 11.17 Cascaded Operation Setting Procedure
Set cascading
Start count
Upper 16 Bits
TCNT_1
TCNT_4
[1]
[2]
[1]
[2]
Set bits TPSC2 to TPSC0 in the channel 1
(channel 4) TCR to B'1111 to select TCNT_2
(TCNT_5) overflow/underflow counting.
Set the CST bit in TSTR for the upper and lower
channel to 1 to start the count operation.
Lower 16 Bits
TCNT_2
TCNT_5