HD6417034AFI20V Renesas Electronics America, HD6417034AFI20V Datasheet - Page 381

• Manufacturer Part Number: HD6417034AFI20V
• Description: MCU 5V 0K I-TEMP PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

13.1
The SuperH microcomputer has a serial communication interface (SCI) with two independent
channels. Both channels are functionally identical. The SCI supports both asynchronous and
synchronous serial communication. It also has a multiprocessor communication function for serial
communication between two or more processors.
13.1.1
SCI features are listed below:
Asynchronous mode
Synchronous mode
Full duplex communication: The transmitting and receiving sections are independent, so the
SCI can transmit and receive simultaneously. Both sections use double buffering, so
continuous data transfer is possible in both the transmit and receive directions.
On-chip baud rate generator with selectable bit rates
Serial data communication is synchronized using a start-stop method in character units.
The SCI can communicate with a universal asynchronous receiver/transmitter (UART), an
asynchronous communication interface adapter (ACIA), or any other chip that employs
standard asynchronous serial communication. It can also communicate with two or more
other processors using the multiprocessor communication function. There are twelve
selectable serial data communication formats.
Data length: seven or eight bits
Stop bit length: one or two bits
Parity: even, odd, or none
Multiprocessor bit: one or none
Receive error detection: parity, overrun, and framing errors
Break detection: by reading the RxD level directly when a framing error occurs
Serial data communication is synchronized with a clock signal. The SCI can communicate
with other chips having a synchronous communication function. There is one serial data
communication format.
Data length: eight bits
Receive error detection: overrun errors
Section 13 Serial Communication Interface (SCI)
Overview
Features
Section 13 Serial Communication Interface (SCI)
Rev. 7.00 Jan 31, 2006 page 353 of 658
REJ09B0272-0700