HD6417034AFI20V Renesas Electronics America, HD6417034AFI20V Datasheet - Page 158

• Manufacturer Part Number: HD6417034AFI20V
• Description: MCU 5V 0K I-TEMP PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 Bus State Controller (BSC)
Table 8.8
A26
0
1
The chip select signal is output only for external accesses. When accessing the on-chip ROM (area
0), on-chip supporting modules (area 5), and on-chip RAM (area 7), the CS0, CS5, and CS7 pins
are not driven low. When accessing DRAM space (area 1), select the RAS and CAS signals with
the pin function controller.
8.3.4
The size of each area is 16 Mbytes, which can be specified with the 24 address bits A23–A0 for 8-
bit spaces and 16-bit spaces alike. Bits A23 and A22, however, output externally only when the
address multiplex function is used in DRAM space (area 1); in all other cases, there is no output,
so the actually accessible area for all areas is the 4 Mbytes that can be specified with the 22 bits
A21–A0. Regardless of the values of A23 and A22, the same 4 Mbytes of actual space is accessed.
As illustrated in figure 8.4 (a), the A23 and A22 bit regions 00, 01, 10 and 11 are called shadows
of actual areas. Shadows are allocated in 4-Mbyte units for both 8-bit and 16-bit bus widths. When
the same addresses H'3200000, H'3600000, H'3A00000 and H'3E00000 are specified for values
A21–A0, as shown in figure 8.4 (b), the same actual space is accessed regardless of the A23 and
A22 bits.
In areas whose bus widths are switchable using the A27 address bit, the shadow of the same actual
space is allocated to both A27 = 0 spaces and A27 = 1 spaces (figure 8.4(a)). When the value of
A27 is changed, the valid AD pins switch from AD15–AD0 to AD7–AD0, but the actual space
accessed remains the same.
The spaces of on-chip ROM (area 0), DRAM (area 1), on-chip supporting modules (area 5), and
on-chip RAM (area 7) have shadows of different sizes from those mentioned above. See section
8.3.5, Area Descriptions, for details.
Rev. 7.00 Jan 31, 2006 page 130 of 658
REJ09B0272-0700
Shadows
A25
0
1
0
1
Address
A26–A24 Bits and Chip Select Signals
A24
0
1
0
1
0
1
0
1
Area Selected
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
Chip Select Pin Driven Low
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS7