HD6417034AFI20V Renesas Electronics America, HD6417034AFI20V Datasheet - Page 146

• Manufacturer Part Number: HD6417034AFI20V
• Description: MCU 5V 0K I-TEMP PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 Bus State Controller (BSC)
Bit 13—RAS Precharge Cycle Count (TPC): TPC selects whether the RAS signal precharge
cycle (T
when 1 is set, a 2-state precharge cycle is inserted.
Bit 13: TPC
0
1
Bit 12—Burst Operation Enable (BE): BE selects whether or not to perform burst operation, a
high-speed page mode. When burst operation is not selected (0), the row address is not compared
but instead is transferred to the DRAM every time and full access is performed. When burst
operation is selected (1), row addresses are compared and burst operation with the same row
address as previously is performed (in this access, no row address is output and the column
address and CAS signal alone are output) (high-speed page mode).
Bit 12: BE
0
1
Bit 11—CAS Duty (CDTY): CDTY selects 35% or 50% of the TC state as the high-level duty
ratio of the signal CAS in short-pitch access. When cleared to 0, the CAS signal high level duty is
50%; when set to 1, it is 35%.
Bit 11: CDTY
0
1
Bit 10—Multiplex Enable Bit (MXE): MXE determines whether or not DRAM row and column
addresses are multiplexed. When cleared to 0, addresses are not multiplexed; when set to 1, they
are multiplexed.
Bit 10: MXE
0
1
Rev. 7.00 Jan 31, 2006 page 118 of 658
REJ09B0272-0700
P
) will be 1 state or 2. When TPC is cleared to 0, a 1-state precharge cycle is inserted;
Description
1-state precharge cycle inserted
2-state precharge cycle inserted
Description
Normal mode: full access
Burst operation: high-speed page mode
Description
CAS signal high level duty cycle is 50% of the T
CAS signal high level duty cycle is 35% of the T
Description
Multiplexing of row and column addresses disabled
Multiplexing of row and column addresses enabled
C
C
state
state
(Initial value)
(Initial value)
(Initial value)
(Initial value)