HD6417034AFI20V Renesas Electronics America, HD6417034AFI20V Datasheet - Page 232

• Manufacturer Part Number: HD6417034AFI20V
• Description: MCU 5V 0K I-TEMP PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 9 Direct Memory Access Controller (DMAC)
In dual address mode transfers, external memory, memory-mapped external devices, on-chip
memory and on-chip supporting modules can be mixed without restriction. Specifically, this
enables the following transfer types:
1. Between external memory and a external memory
2. Between external memory and a memory-mapped external device
3. Between a memory-mapped external devices
4. Between external memory and on-chip memory
5. Between external memory and an on-chip supporting module (excluding the DMAC)
6. Between memory-mapped external device and on-chip memory
7. Between memory-mapped external device and an on-chip supporting module (excluding the
8. On-chip memory to on-chip memory
9. Between on-chip memory and an on-chip supporting module (excluding the DMAC)
10. Between on-chip supporting modules (excluding the DMAC)
Transfer requests can be auto requests, external requests, or on-chip supporting module requests.
When the transfer request source is either the SCI or A/D converter, however, either the data
destination or source must be the SCI or A/D converter (table 9.4). In dual address mode, DACK
is output in read or write cycles other than for internal memory and external supporting modules.
CHCR controls the cycle in which DACK is output.
Figure 9.9 shows the DMA transfer timing in dual address mode.
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DMAC)
SuperH microcomputer
Figure 9.8 Data Flow in Dual Address Mode
DMAC
1: Read cycle
2: Write cycle
External data bus
: Data flow
2
1
External
External
memory
memory