HD6417034AFI20V Renesas Electronics America, HD6417034AFI20V Datasheet - Page 125

MCU 5V 0K I-TEMP PB-FREE 112-QFP

HD6417034AFI20V

Manufacturer Part Number
HD6417034AFI20V
Description
MCU 5V 0K I-TEMP PB-FREE 112-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet

Specifications of HD6417034AFI20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417034AFI20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
7.1
The SuperH microcomputer has a built-in clock pulse generator (CPG) that supplies the chip and
external devices with a clock pulse. The CPG makes the chip run at the oscillation frequency of
the crystal resonator. The CPG consists of an oscillator and a duty cycle correction circuit (figure
7.1). The CPG can be made to generate a clock signal by connecting it to a crystal resonator or by
inputting an external clock. (The CPG is halted in standby mode.)
7.2
Clock pulses can be supplied from a connected crystal resonator or an external clock.
7.2.1
Circuit Configuration: A crystal resonator can be connected as shown in figure 7.2. Use the
damping resistance Rd shown in table 7.1. Use an AT-cut parallel resonating crystal with a
frequency equal to the system clock (CK) frequency. Connect load capacitors (C
shown in the figure. The clock pulse produced by the crystal resonator and internal pulse generator
is sent to the duty cycle correction circuit where its duty cycle is corrected. It is then supplied to
the chip and to external devices.
System clock
Overview
Clock Source
Connecting a Crystal Resonator
EXTAL
XTAL
Section 7 Clock Pulse Generator (CPG)
CK
Figure 7.1 Block Diagram of Clock Pulse Generator
Oscillator
correction circuit
Duty cycle
Section 7 Clock Pulse Generator (CPG)
Rev. 7.00 Jan 31, 2006 page 97 of 658
CPG
REJ09B0272-0700
L1
Internal
clock ( )
and C
L2
) as

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