D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 44

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Section 22 Power-Down Modes
Figure 22.1
Figure 22.2
Figure 22.3
Section 24 Electrical Characteristics
Figure 24.1
Figure 24.2
Figure 24.3
Figure 24.4 (1) Oscillation Stabilization Timing........................................................................ 872
Figure 24.4 (2) Oscillation Stabilization Timing........................................................................ 873
Figure 24.5
Figure 24.6
Figure 24.7
Figure 24.8
Figure 24.9
Figure 24.10 Basic Bus Timing: Two-State Access (CS Assertion Period Extended).............. 882
Figure 24.11 Basic Bus Timing: Three-State Access (CS Assertion Period Extended)............ 883
Figure 24.12 Burst ROM Access Timing: One-State Burst Access .......................................... 884
Figure 24.13 Burst ROM Access Timing: Two-State Burst Access ......................................... 885
Figure 24.14 DRAM Access Timing: Two-State Access.......................................................... 886
Figure 24.15 DRAM Access Timing: Two-State Access, One Wait ........................................ 887
Figure 24.16 DRAM Access Timing: Two-State Burst Access ................................................ 888
Figure 24.17 DRAM Access Timing: Three-State Access (RAST = 1).................................... 889
Figure 24.18 DRAM Access Timing: Three-State Access, One Wait ...................................... 890
Figure 24.19 DRAM Access Timing: Three-State Burst Access .............................................. 891
Figure 24.20 CAS-Before-RAS Refresh Timing ...................................................................... 892
Figure 24.21 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion).......................... 892
Figure 24.22 Self-Refresh Timing (Return from Software Standby Mode: RAST = 0) ........... 893
Figure 24.23 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1) ........... 893
Figure 24.24 External Bus Release Timing............................................................................... 894
Figure 24.25 External Bus Request Output Timing .................................................................. 894
Figure 24.26 Synchronous DRAM Basic Access Timing (CAS Latency 2)............................. 895
Figure 24.27 Synchronous DRAM Self-Refresh Timing .......................................................... 896
Figure 24.28 Read Data: Two-State Expansion (CAS Latency 2) ............................................ 897
Figure 24.29 DMAC and EXDMAC Single Address Transfer Timing: Two-State Access ..... 899
Figure 24.30 DMAC and EXDMAC Single Address Transfer Timing: Three-State Access ... 900
Figure 24.31 DMAC and EXDMAC TEND/ETEND Output Timing ...................................... 901
Figure 24.32 DMAC and EXDMAC DREQ/EDREQ Input Timing ........................................ 901
Figure 24.33 EXDMAC EDRAK Output Timing..................................................................... 901
Figure 24.34 I/O Port Input/Output Timing .............................................................................. 903
Rev. 3.00 Mar 17, 2006 page xlii of l
Mode Transitions ................................................................................................. 821
Software Standby Mode Application Example.................................................... 829
Hardware Standby Mode Timing......................................................................... 830
Output Load Circuit ............................................................................................. 870
System Clock Timing .......................................................................................... 871
SDRAM Timing ................................................................................................ 872
Reset Input Timing .............................................................................................. 874
Interrupt Input Timing ......................................................................................... 875
Basic Bus Timing: Two-State Access.................................................................. 879
Basic Bus Timing: Three-State Access................................................................ 880
Basic Bus Timing: Three-State Access, One Wait............................................... 881