D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 390

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Section 8 EXDMA Controller
8.3
The EXDMAC has the following registers.
8.3.1
EDSAR is a 32-bit readable/writable register that specifies the transfer source address. An address
update function is provided that updates the register contents to the next transfer source address
each time transfer processing is performed. In single address mode, the EDSAR value is ignored
when a device with DACK is specified as the transfer source. The upper 8 bits of EDSAR are
reserved; they are always read as 0 and cannot be modified.
EDSAR can be read at all times by the CPU. When reading EDSAR for a channel on which
EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write
to EDSAR for a channel on which EXDMA transfer is in progress. The initial values of EDSAR
are undefined.
Rev. 3.00 Mar 17, 2006 page 338 of 926
REJ09B0283-0300
EXDMA source address register_0 (EDSAR_0)
EXDMA destination address register_0 (EDDAR_0)
EXDMA transfer count register_0 (EDTCR_0)
EXDMA mode control register_0 (EDMDR_0)
EXDMA address control register_0 (EDACR_0)
EXDMA source address register_1 (EDSAR_1)
EXDMA destination address register_1 (EDDAR_1)
EXDMA transfer count register_1 (EDTCR_1)
EXDMA mode control register_1 (EDMDR_1)
EXDMA address control register_1 (EDACR_1)
EXDMA source address register_2 (EDSAR_2)
EXDMA destination address register_2 (EDDAR_2)
EXDMA transfer count register_2 (EDTCR_2)
EXDMA mode control register_2 (EDMDR_2)
EXDMA address control register_2 (EDACR_2)
EXDMA source address register_3 (EDSAR_3)
EXDMA destination address register_3 (EDDAR_3)
EXDMA transfer count register_3 (EDTCR_3)
EXDMA mode control register_3 (EDMDR_3)
EXDMA address control register_3 (EDACR_3)
Register Descriptions
EXDMA Source Address Register (EDSAR)