D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 325

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Bit
13
12
11
10
9
8
Bit Name
SAE1
SAE0
DTA1B
DTA1A
DTA0B
DTA0A
Initial Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Single Address Enable 1
Specifies whether channel 1B is to be used for
transfer in dual address mode or single address
mode. This bit is invalid in full address mode.
0: Dual address mode
1: Single address mode
Single Address Enable 0
Specifies whether channel 0B is to be used for
transfer in dual address mode or single address
mode. This bit is invalid in full address mode.
0: Dual address mode
1: Single address mode
Data Transfer Acknowledge 1B
Data Transfer Acknowledge 1A
Data Transfer Acknowledge 0B
Data Transfer Acknowledge 0A
These bits enable or disable clearing when
DMA transfer is performed for the internal
interrupt source selected by the DTF3 to DTF0
bits in DMACR.
It the DTA bit is set to 1 when DTE = 1, the
internal interrupt source is cleared automatically
by DMA transfer. When DTE = 1 and DTA = 1,
the internal interrupt source does not issue an
interrupt request to the CPU or DTC.
If the DTA bit is cleared to 0 when DTE = 1, the
internal interrupt source is not cleared when a
transfer is performed, and can issue an
interrupt request to the CPU or DTC in parallel.
In this case, the interrupt source should be
cleared by the CPU or DTC transfer.
When DTE = 0, the internal interrupt source
issues an interrupt request to the CPU or DTC
regardless of the DTA bit setting.
Rev. 3.00 Mar 17, 2006 page 273 of 926
Section 7 DMA Controller (DMAC)
REJ09B0283-0300