D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 174

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Section 6 Bus Controller (BSC)
A block diagram of the bus controller is shown in figure 6.1.
Rev. 3.00 Mar 17, 2006 page 122 of 926
REJ09B0283-0300
Legend:
ABWCR
ASTCR
WTCRAH, WTCRAL,
WTCRBH, and WTCRBL : Wait control registers AH, AL, BH, and BL
RDNCR
CSACRH and CSACRL : CS assertion period control registers
BROMCRH
Note: * DRACCR is an 8-bit register in the H8S/2678 Group and a 16-bit register in the H8S/2678R Group.
EXDMAC address bus
Internal address bus
Internal bus master bus acknowledge signal
Internal bus master bus request signal
EXDMAC bus acknowledge signal
DMAC bus acknowledge signal
CPU bus acknowledge signal
DTC bus acknowledge signal
EXDMAC bus request signal
: Bus width control register
: Access state control register
: Read strobe timing control register
: Area 0 burst ROM interface control register
Internal bus control signals
DMAC bus request signal
CPU bus request signal
DTC bus request signal
Figure 6.1 Block Diagram of Bus Controller
Internal data bus
Address
selector
External bus
Internal bus
BROMCRH BROMCRL
External bus controller
Control registers
WTCRAH WTCRAL
WTCRBH WTCRBL
CSACRH
Internal bus controller
arbiter
arbiter
ABWCR
RDNCR
Area decoder
BROMCRL : Area 1 burst ROM interface control register
BCR
DRAMCR : DRAM control register
DRACCR : DRAM access control register
REFCR
RTCNT
RTCOR
BCR
CSACRL
ASTCR
: Bus control register
: Refresh control register
: Refresh timer counter
: Refresh time constant register
RTCNT
DRAMCR
DRACCR *
REFCR
CS7 to CS0
External bus
control signals
WAIT
BREQ
BACK
BREQO
RTCOR