DF2370VFQ34V Renesas Electronics America, DF2370VFQ34V Datasheet - Page 93
![IC H8S/2370 MCU FLASH 144-LQFP](/photos/12/41/124170/df2370vfq34v_sml.jpg)
DF2370VFQ34V
Manufacturer Part Number
DF2370VFQ34V
Description
IC H8S/2370 MCU FLASH 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2370VFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2370VFQ34V
Manufacturer:
Exar
Quantity:
67
Company:
Part Number:
DF2370VFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 93 of 1208
- Download datasheet (8Mb)
Type
Bus
control
Symbol
RAS/
RAS2
RAS3 to
RAS5
RAS *
CAS *
WE *
WAIT
1
1
1
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2378R
0.18μm
F-ZTAT Group
(LQFP-144)
109, 110,
35, 36
109
110
35
84
H8S/2378
0.18μm
F-ZTAT Group,
H8S/2378R
0.18μm
F-ZTAT Group
(LGA-145)
A12,
A13,
L1,
M1
A12
A13
L1
J11
Pin No.
H8S/2377
H8S/2377R
109, 110,
35, 36
109
110
35
84
Rev.7.00 Mar. 18, 2009 page 25 of 1136
H8S/2375
H8S/2373
H8S/2375R
H8S/2373R I/O
109, 110,
35, 36
109
110
35
84
Output Row address strobe
Output Row address strobe
Output Column address
Output Write enable signal
Input
Section 1 Overview
REJ09B0109-0700
Function
signal for the
synchronous DRAM
interface.
RAS signal is a row
address strobe
signal when areas 2
to 5 are set to the
continuous DRAM
space.
signal for the
synchronous DRAM
of the synchronous
DRAM interface.
strobe signal for the
synchronous DRAM
of the synchronous
DRAM interface.
for the synchronous
DRAM of the
synchronous DRAM
interface.
Requests insertion
of a wait state in the
bus cycle when
accessing external
3-state address
space.
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