DF2370VFQ34V Renesas Electronics America, DF2370VFQ34V Datasheet - Page 505
![IC H8S/2370 MCU FLASH 144-LQFP](/photos/12/41/124170/df2370vfq34v_sml.jpg)
DF2370VFQ34V
Manufacturer Part Number
DF2370VFQ34V
Description
IC H8S/2370 MCU FLASH 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2370VFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2370VFQ34V
Manufacturer:
Exar
Quantity:
67
Company:
Part Number:
DF2370VFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 505 of 1208
- Download datasheet (8Mb)
Section 9 Data Transfer Controller (DTC)
9.5
Operation
The DTC stores register information in the on-chip RAM. When activated, the DTC reads register
information that is already stored in the on-chip RAM and transfers data on the basis of that
register information. After the data transfer, it writes updated register information back to the on-
chip RAM. Pre-storage of register information in the on-chip RAM makes it possible to transfer
data over any required number of channels. There are three transfer modes: normal mode, repeat
mode, and block transfer mode. Setting the CHNE bit to 1 makes it possible to perform a number
of transfers with a single activation (chain transfer). A setting can also be made to have chain
transfer performed only when the transfer counter value is 0. This enables DTC re-setting to be
performed by the DTC itself.
The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed.
Figure 9.5 shows a flowchart of DTC operation, and table 9.3 summarizes the chain transfer
conditions (combinations for performing the second and third transfers are omitted).
Rev.7.00 Mar. 18, 2009 page 437 of 1136
REJ09B0109-0700
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