DF2370VFQ34V Renesas Electronics America, DF2370VFQ34V Datasheet - Page 922
![IC H8S/2370 MCU FLASH 144-LQFP](/photos/12/41/124170/df2370vfq34v_sml.jpg)
DF2370VFQ34V
Manufacturer Part Number
DF2370VFQ34V
Description
IC H8S/2370 MCU FLASH 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2370VFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2370VFQ34V
Manufacturer:
Exar
Quantity:
67
Company:
Part Number:
DF2370VFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 922 of 1208
- Download datasheet (8Mb)
Section 20 Flash Memory (0.35-μm F-ZTAT Version)
20.8
There are three kinds of flash memory program/erase protection: hardware protection, software
protection, and error protection.
20.8.1
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted because of a transition to reset (including an overflow reset by the WDT) or
standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2
(FLMCR2), erase block register 1 (EBR1), and erase block register 2 (EBR2) are initialized. In a
reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation
stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the
RES pulse width specified in the AC Characteristics section.
20.8.2
Protection can be implemented against programming/erasing of all flash memory blocks by
clearing the SWE bit in FLMCR1 to 0 by software (these operations must be executed in the on-
chip RAM or external memory). When protection is in effect, setting the P or E bit in FLMCR1
does not cause a transition to program mode or erase mode. By setting the erase block register 1
(EBR1) and erase block register 2 (EBR2), erase protection can be set for individual blocks.
When EBR1 and EBR2 are set to H'00, erase protection is set for all blocks.
20.8.3
In error protection, an error is detected when the CPU’s runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is forcibly aborted. Aborting the program/erase
operation prevents damage to the flash memory due to overprogramming or overerasing.
When the following errors are detected during programming/erasing of flash memory, the FLER
bit in FLMCR2 is set to 1, and the error protection state is entered.
• When flash memory is read during programming/erasing (including a vector read or instruction
• When an exception handling (excluding a reset) is started during programming/erasing
• When a SLEEP instruction is executed during programming/erasing
• When the CPU releases the bus during programming/erasing
Rev.7.00 Mar. 18, 2009 page 854 of 1136
REJ09B0109-0700
fetch)
Program/Erase Protection
Hardware Protection
Software Protection
Error Protection
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