M38513E4FP#U0 Renesas Electronics America, M38513E4FP#U0 Datasheet - Page 60

• Manufacturer Part Number: M38513E4FP#U0
• Description: IC 740 MCU ROM 16K 42SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38513E4FP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 42-SSOP
• Package: 42SSOP
• Family Name: 740
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: I2C-BUS
• On-chip Adc: 5-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

3851 Group
Functions To Inhibit Rewriting Flash Memory
Version
To prevent the contents of internal flash memory from being read
out or rewritten easily, this MCU incorporates a ROM code protect
function for use in parallel I/O mode and an ID code check func-
tion for use in standard serial I/O mode.
The ROM code protect function is the function to inhibit reading
out or modifying the contents of internal flash memory by using
the ROM code protect control (address FFDB
mode. Figure 63 shows the ROM code protect control (address
FFDB
If one or both of the pair of ROM Code Protect Bits is set to “0”,
Fig. 63 Structure of ROM code protect control
Rev.1.01
ROM Code Protect Function (in Parallel I/O Mode)
16
). (This address exists in the User ROM area.)
Oct 15, 2003
b 7
Notes 1: This area is on the ROM in the mask ROM version.
(Built-in 24 KB or more ROM)
2: When ROM code protect is turned on, the internal flash memory is protected
3: When ROM code protect level 2 is turned on, ROM code readout by a shipment
4: The ROM code protect reset bits can be used to turn off ROM code protect level 1
against readout or modification in parallel I/O mode.
inspection LSI tester, etc. also is inhibited.
and ROM code protect level 2. However, since these bits cannot be modified in
parallel I/O mode, they need to be rewritten in standard serial I/O mode or CPU
rewrite mode.
page 58 of 89
1
b 0
1
16
) in parallel I/O
R O M c o d e p r o t e c t c o n t r o l r e g i s t e r ( a d d r e s s F F D B
R O M C P
R e s e r v e d b i t s ( “ 1 ” a t r e a d / w r i t e )
R O M c o d e p r o t e c t l e v e l 2 s e t b i t s ( R O M C P 2 ) (N o t e s 2 , 3)
R O M c o d e p r o t e c t r e s e t b i t s
R O M c o d e p r o t e c t l e v e l 1 s e t b i t s ( R O M C P 1 ) (N o t e 2)
b 3 b 2
0 0 : P r o t e c t e n a b l e d
0 1 : P r o t e c t e n a b l e d
1 0 : P r o t e c t e n a b l e d
1 1 : P r o t e c t d i s a b l e d
b 5 b 4
0 0 : P r o t e c t r e m o v e d
0 1 : P r o t e c t s e t b i t s e f f e c t i v e
1 0 : P r o t e c t s e t b i t s e f f e c t i v e
1 1 : P r o t e c t s e t b i t s e f f e c t i v e
b 7 b 6
0 0 : P r o t e c t e n a b l e d
0 1 : P r o t e c t e n a b l e d
1 0 : P r o t e c t e n a b l e d
1 1 : P r o t e c t d i s a b l e d
the ROM code protect is turned on, so that the contents of internal
flash memory are protected against readout and modification. The
ROM code protect is implemented in two levels. If level 2 is se-
lected, the flash memory is protected even against readout by a
shipment inspection LSI tester, etc. When an attempt is made to
select both level 1 and level 2, level 2 is selected by default.
If both of the two ROM Code Protect Reset Bits are set to “00”, the
ROM code protect is turned off, so that the contents of internal
flash memory can be read out or modified. Once the ROM code
protect is turned on, the contents of the ROM Code Protect Reset
Bits cannot be modified in parallel I/O mode. Use the serial I/O or
CPU rewrite mode to rewrite the contents of the ROM Code Pro-
tect Reset Bits.
(N o t e 4)
1 6
) (N o t e 1)