DF36054GFPJ Renesas Electronics America, DF36054GFPJ Datasheet - Page 293

MCU 3/5V 32K J-TEMP POR&LVD 64-Q

DF36054GFPJ

Manufacturer Part Number
DF36054GFPJ
Description
MCU 3/5V 32K J-TEMP POR&LVD 64-Q
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of DF36054GFPJ

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F36054GFPJ
HD64F36054GFPJ
14.3.7
SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared.
Bit
7
6
5
4
Bit Name
TDRE
RDRF
OER
FER
Serial Status Register (SSR)
Initial
Value
1
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
[Clearing conditions]
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
[Clearing conditions]
Overrun Error
[Setting condition]
[Clearing condition]
Framing Error
[Setting condition]
[Clearing condition]
When the TE bit in SCR3 is 0
When data is transferred from TDR to TSR
When 0 is written to TDRE after reading TDRE = 1
When the transmit data is written to TDR
When serial reception ends normally and receive data
is transferred from RSR to RDR
When 0 is written to RDRF after reading RDRF = 1
When data is read from RDR
When an overrun error occurs in reception
When 0 is written to OER after reading OER = 1
When a framing error occurs in reception
When 0 is written to FER after reading FER = 1
Section 14 Serial Communication Interface 3 (SCI3)
Rev. 4.00 Mar. 15, 2006 Page 259 of 556
REJ09B0026-0400

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