DF36054GFPJ Renesas Electronics America, DF36054GFPJ Datasheet - Page 105

MCU 3/5V 32K J-TEMP POR&LVD 64-Q

DF36054GFPJ

Manufacturer Part Number
DF36054GFPJ
Description
MCU 3/5V 32K J-TEMP POR&LVD 64-Q
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of DF36054GFPJ

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F36054GFPJ
HD64F36054GFPJ
4.2
When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an
interrupt request to the CPU. The ABIF bit in ABRKSR is set to 1 by the combination of the
address set in BAR, the data set in BDR, and the conditions set in ABRKCR. When the interrupt
request is accepted, interrupt exception handling starts after the instruction being executed ends.
The address break interrupt is not masked by the I bit in CCR of the CPU.
Figures 4.2 show the operation examples of the address break interrupt setting.
Operation
When the address break is specified in instruction execution cycle
Register setting
• ABRKCR = H'80
• BAR = H'025A
Address
bus
Interrupt
request
Figure 4.2 Address Break Interrupt Operation Example (1)
prefetch
instruc-
NOP
0258
tion
prefetch
instruc-
NOP
Program
*
tion
025A
0258
025A
025C
0260
0262
:
Interrupt acceptance
prefetch
instruc-
tion 1
NOP
NOP
MOV.W @H'025A,R0
NOP
NOP
MOV
025C
:
prefetch
instruc-
tion 2
MOV
025E
processing
Internal
Underline indicates the address
to be stacked.
Rev. 4.00 Mar. 15, 2006 Page 71 of 556
SP-2
Stack save
SP-4
Section 4 Address Break
REJ09B0026-0400

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