DF36034GFPJ Renesas Electronics America, DF36034GFPJ Datasheet - Page 378

MCU 3/5V 32K J-TEMP POR&LVD 64-L

DF36034GFPJ

Manufacturer Part Number
DF36034GFPJ
Description
MCU 3/5V 32K J-TEMP POR&LVD 64-L
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of DF36034GFPJ

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F36034GFPJ
HD64F36034GFPJ
Section 15 Controller Area Network for Tiny (TinyCAN)
15.6
The TinyCAN has the following interrupt requests. These interrupts can be masked except for a
reset processing interrupt caused by powering on. To mask them, the Mailbox interrupt mask
register (MBIMR) and interrupt mask register (IMR) are used. Since these interrupt requests are
allocated to the common vector addresses, their sources need to be identified by flags.
Table 15.4 Interrupt Requests
When TEC or REC becomes 128 after incrementing or decrementing, note that the error passive
(EPI) flag issues an interrupt request. When REC or TEC becomes 96 after incrementing or
decrementing, note that the receive overload warning (ROWI) flag or transmit overload warning
(TOWI) flag issues an interrupt request, respectively.
Rev. 4.00 Mar. 15, 2006 Page 344 of 556
REJ09B0026-0400
Interrupt Request
Wakeup
Unread message
Mailbox empty
Overload frame transmission
Bus off
Error passive
Receive overload warning
Transmit overload warning
Remote frame request
Receive message
Reset/Halt
Interrupt Requests
Abbreviation
WUPI
OVRI
EMPI
OVLI
BOFI
EPI
ROWI
TOWI
RFRI
DFRI
RHI
Interrupt Condition
When falling edge of HRXD is detected in LSI
standby mode
When new message is received while MBIMR
corresponding to receive message is 0 and
RXPR or RFPR is 1
When TXPR is cleared to 0 by completion of
transmission or completion of transmission
cancellation
When overload frame is transmitted
When TEC
times in bus off state
When TEC
When REC
When TEC
When remote frame is received and
corresponding MBIMR is 0
When message reception is completed and
corresponding MBIMR is 0
When processing is completed after software
reset request (RSTRQ) or halt mode request
(HLTRQ) is issued
256 or 11 bits are received 128
128 or REC
96
96
128

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