DF36034GFPJ Renesas Electronics America, DF36034GFPJ Datasheet - Page 213

• Manufacturer Part Number: DF36034GFPJ
• Description: MCU 3/5V 32K J-TEMP POR&LVD 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36034GFPJ

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F36034GFPJ; HD64F36034GFPJ

12.3.9
The TCR registers select a TCNT counter clock, an edge when an external clock is selected, and
counter clearing sources. Timer Z has a total of two TCR registers, one for each channel.
Notes: 1. When GR functions as an output compare register, TCNT is cleared by compare match.
Bit
7
6
5
4
3
2
1
0
2. Synchronous operation is set by TMDR.
3. X: Don’t care
Bit Name
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
Timer Control Register (TCR)
When GR functions as input capture, TCNT is cleared by input capture.
Initial
Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Counter Clear 2 to 0
000: Disables TCNT clearing
001: Clears TCNT by GRA compare match/input
010: Clears TCNT by GRB compare match/input
011: Synchronization clear; Clears TCNT in synchronous
000: Disables TCNT clearing
001: Clears TCNT by GRC compare match/input
010: Clears TCNT by GRD compare match/input
011: Synchronization clear; Clears TCNT in synchronous
Clock Edge 1 and 0
00: Count at rising edge
01: Count at falling edge
1X: Count at both edges
Time Prescaler 2 to 0
000: Internal clock: count by
001: Internal clock: count by /2
010: Internal clock: count by /4
011: Internal clock: count by /8
1XX: External clock: count by FTIOA0 (TCLK) pin input
capture*
capture*
with counter clearing of the other channel’s timer*
capture*
capture*
with counter clearing of the other channel’s timer*
1
1
1
1
Rev. 4.00 Mar. 15, 2006 Page 179 of 556
Section 12 Timer Z
REJ09B0026-0400
2
2