DF36034GFPJ Renesas Electronics America, DF36034GFPJ Datasheet - Page 276

• Manufacturer Part Number: DF36034GFPJ
• Description: MCU 3/5V 32K J-TEMP POR&LVD 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36034GFPJ

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F36034GFPJ; HD64F36034GFPJ

Section 12 Timer Z
Note on Clearing TSR Flag: When a specific flag in TSR is cleared, a combination of the BCLR
or MOV instructions is used to read 1 from the flag and then write 0 to the flag. However, if
another bit is set during this processing, the bit may also be cleared simultaneously. To avoid this,
the following processing that does not use the BCLR instruction must be executed. Note that this
note is only applied to the F-ZTAT version. This problem has already been solved in the mask
ROM version.
Note on Writing to the TOA0 to TOD0 Bits and the TOA1 to TOD1 Bits in TOCR:
The TOA0 to TOD0 bits and the TOA1 to TOD1 bits in TOCR decide the value of the FTIO pin,
which is output until the first compare match occurs. Once a compare match occurs and this
compare match changes the values of FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 output, the
values of the FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 pin output and the values read from the
TOA0 to TOD0 and TOA1 to TOD1 bits may differ. Moreover, when the writing to TOCR and
the generation of the compare match A0 to D0 and A1 to D1 occur at the same timing, the writing
to TOCR has the priority. Thus, output change due to the compare match is not reflected to the
FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 pins. Therefore, when bit manipulation instruction is
used to write to TOCR, the values of the FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 pin output
may result in an unexpected result. When TOCR is to be written to while compare match is
operating, stop the counter once before accessing to TOCR, read the port 6 state to reflect the
values of FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 output, to TOA0 to TOD0 and TOA1 to
TOD1, and then restart the counter. Figure 12.59 shows an example when the compare match and
the bit manipulation instruction to TOCR occur at the same timing.
Rev. 4.00 Mar. 15, 2006 Page 242 of 556
REJ09B0026-0400
Example: When clearing bit 4 (OVF) in TSR
MOV.B @TSR,R0L
MOV.B #B'11101111, R0L
MOV.B R0L,@TSR
the other bits are all set to 1.
Only the bit to be cleared is 0 and