DF36034GFPJ Renesas Electronics America, DF36034GFPJ Datasheet - Page 357

• Manufacturer Part Number: DF36034GFPJ
• Description: MCU 3/5V 32K J-TEMP POR&LVD 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36034GFPJ

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F36034GFPJ; HD64F36034GFPJ

15.4.3
The message data is configured as eight 8-bit registers for a single Mailbox. The transmit and
receive data are stored from byte 0 in the low-to-high order. The TinyCAN has four sets of
message data. The bit order on the CAN bus is from 1 to 8 bytes. Since MDn0 to MDn7 (n = 0 to
3) are in RAM, initial values are undefined after power-on. Be sure to initialize these bits by
writing 0 or 1.
Register
Name
LAFMHn1
(n = 0 to 3)
LAFMHn0
(n = 0 to 3)
Message Data (MDn0 to MDn7 [n = 0 to 3])
Mailbox 0
Mailbox 1
Mailbox 2
Mailbox 3
Bit
4 to 2
1, 0
7 to 0
MD0[0]
MD1[0]
MD2[0]
MD3[0]
Bit Name
—
LAFMHn1,
LAFMHn0
LAFMHn15 to
LAFMHn8
Figure 15.3 Message Data Configuration
MD0[1]
MD1[1]
MD2[1]
MD3[1]
MD0[2]
MD1[2]
MD2[2]
MD3[2]
R/W
—
R/W
R/W
MD0[3]
MD1[3]
MD2[3]
MD3[3]
Description
Reserved
These bits are always read as 0.
Filter mask for bits 17 and 16 of the extended
identifier.
0: Receive message is stored in RXn because the
1: Receive message is stored in RXn regardless of
Filter mask for bits 10 to 3 of the standard
identifier.
0: Receive message is stored in RXn because the
1: Receive message is stored in RXn regardless of
Section 15 Controller Area Network for Tiny (TinyCAN)
RXn message identifier bits match the receive
message identifier bits
whether the RXn message identifier bits match
the receive message identifier bits
RXn message identifier bits match the receive
message identifier bits
whether the RXn message identifier bits match
the receive message identifier bits
MD0[4]
MD1[4]
MD2[4]
MD3[4]
Rev. 4.00 Mar. 15, 2006 Page 323 of 556
MD0[5]
MD1[5]
MD2[5]
MD3[5]
MD0[6]
MD1[6]
MD2[6]
MD3[6]
MD0[7]
MD1[7]
MD2[7]
MD3[7]
REJ09B0026-0400