DF36034GFPJ Renesas Electronics America, DF36034GFPJ Datasheet - Page 312
![MCU 3/5V 32K J-TEMP POR&LVD 64-L](/photos/28/61/286100/64-lqfp__plqp0064kb-a_sml.jpg)
DF36034GFPJ
Manufacturer Part Number
DF36034GFPJ
Description
MCU 3/5V 32K J-TEMP POR&LVD 64-L
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.DF36057GFZV.pdf
(594 pages)
Specifications of DF36034GFPJ
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F36034GFPJ
HD64F36034GFPJ
HD64F36034GFPJ
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Section 14 Serial Communication Interface 3 (SCI3)
14.5
Figure 14.9 shows the general format for clocked synchronous communication. In clocked
synchronous mode, data is transmitted or received synchronous with clock pulses. A single
character in the transmit data consists of the 8-bit data starting from the LSB. In clocked
synchronous serial communication, data on the transmission line is output from one falling edge of
the synchronization clock to the next. In clocked synchronous mode, the SCI3 receives data in
synchronous with the rising edge of the synchronization clock. After 8-bit data is output, the
transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor
bit is added. Inside the SCI3, the transmitter and receiver are independent units, enabling full-
duplex communication through the use of a common clock. Both the transmitter and the receiver
also have a double-buffered structure, so data can be read or written during transmission or
reception, enabling continuous data transfer.
14.5.1
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCK3 pin can be selected, according to the setting of the COM
bit in SMR and CKE0 and CKE1 bits in SCR3. When the SCI3 is operated on an internal clock,
the synchronization clock is output from the SCK3 pin. Eight synchronization clock pulses are
output in the transfer of one character, and when no transfer is performed the clock is fixed high.
14.5.2
Before transmitting and receiving data, the SCI3 should be initialized as described in a sample
flowchart in figure 14.4.
Rev. 4.00 Mar. 15, 2006 Page 278 of 556
REJ09B0026-0400
Operation in Clocked Synchronous Mode
Clock
SCI3 Initialization
Synchronization
clock
Serial data
Note: * High except in continuous transfer
Figure 14.9 Data Format in Clocked Synchronous Communication
Don’t care
*
LSB
Bit 0
One unit of transfer data (character or frame)
Bit 1
Bit 2
Bit 3
8-bit
Bit 4
Bit 5
Bit 6
MSB
Bit 7
Don’t care
*
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