S912XEP100J5MAG Freescale Semiconductor, S912XEP100J5MAG Datasheet - Page 380

• Manufacturer Part Number: S912XEP100J5MAG
• Description: MCU 64K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S912XEP100J5MAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 10 XGATE (S12XGATEV3)
10.4.5
Upon detecting an error condition caused by erratic application code, the XGATE module will
immediately terminate program execution and trigger a non-maskable interrupt to the S12X_CPU. There
are three error conditions:
All opcodes which are not listed in section
opcode fetches as well as illegal load and store accesses are defined on chip level. Refer to the
S12X_MMC Section for a detailed information.
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indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
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•
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Execution of an illegal opcode
Illegal opcode fetches
Illegal load or store accesses
Software Error Detection
When executing a branch (BCC, BCS,...), a jump (JAL) or an RTS
instruction, the XGATE prefetches and discards the opcode of the following
instruction. The XGATE will perform its software error handling actions
(see above) if this opcode fetch is illegal.
Figure 10-25. Algorithm for Locking and Releasing Semaphores
S12X_CPU
1 ⇒ XGSEM[n]
0 ⇒ XGSEM[n]
XGSEM[n] 1?
sequence
critical
.........
.........
code
MC9S12XE-Family Reference Manual , Rev. 1.23
Section 10.8, “Instruction Set”
NOTE
XGATE
sequence
critical
CSEM
SSEM
.........
.........
BCC?
code
are illegal opcodes. Illegal
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