S912XEP100J5MAG Freescale Semiconductor, S912XEP100J5MAG Datasheet - Page 142

• Manufacturer Part Number: S912XEP100J5MAG
• Description: MCU 64K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S912XEP100J5MAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime.
Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.46
142
Address 0x0259
Write:Never, writes to this register have no effect.
Field
PTP
PTP
PTP
PTP
Reset
3
2
1
0
W
R
Port P general purpose input/output data—Data Register
Port P pin 3 is associated with the PWM output channel 3 and the SS signal of SPI1.
The PWM function takes precedence over the SPI1 and the general purpose I/O function if the PWM channel 3 is
enabled. The SPI1 function takes precedence of the general purpose I/O function if the routed SPI1 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
Port P general purpose input/output data—Data Register
Port P pin 2 is associated with the PWM output channel 2 and the SCK signal of SPI1.
The PWM function takes precedence over the SPI1 and the general purpose I/O function if the PWM channel 2 is
enabled. The SPI1 function takes precedence of the general purpose I/O function if the routed SPI1 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
Port P general purpose input/output data—Data Register
Port P pin 1 is associated with the PWM output channel 1 and the MOSI signal of SPI1.
The PWM function takes precedence over the SPI1 and the general purpose I/O function if the PWM channel 1 is
enabled. The SPI1 function takes precedence of the general purpose I/O function if the routed SPI1 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
Port P general purpose input/output data—Data Register
Port P pin 0 is associated with the PWM output channel 0 and the MISO signal of SPI1.
The PWM function takes precedence over the SPI1 and the general purpose I/O function if the PWM channel 0 is
enabled. The SPI1 function takes precedence of the general purpose I/O function if the routed SPI1 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
PTIP7
Port P Input Register (PTIP)
u
7
= Unimplemented or Reserved
PTIP6
Table 2-41. PTP Register Field Descriptions (continued)
u
6
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 2-44. Port P Input Register (PTIP)
PTIP5
u
5
PTIP4
u
4
Description
u = Unaffected by reset
PTIP3
3
u
PTIP2
u
2
Freescale Semiconductor
PTIP1
u
1
Access: User read
PTIP0
u
0
(1)