HD6417020SX20IV Renesas Electronics America, HD6417020SX20IV Datasheet - Page 254

• Manufacturer Part Number: HD6417020SX20IV
• Description: SH 1 CORE 32B MPU, 20MHZ/5V, 100
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SX20IV

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Note: Undefined
• Bit 7 (reserved): Bit 7 is read as undefined. The write value should be 0 or 1.
• Bits 6 and 5 (counter clear 1 and 0 (CCLR1 and CCLR0)): CCLR1 and CCLR0 select the
Bit 6:
CCLR1
0
1
Notes: 1. When GR is functioning as an output compare register, TCNT is cleared upon a
• Bits 4 and 3 (external clock edge 1/0 (CKEG1 and CKEG0)): CKEG1 and CKEG0 select
Bit 4:
CKEG
1
0
1
• Bits 2–0 (timer prescalar 2–0 (TPS2–TPS0)): TPS2–TPS0 select the counter clock source.
236 RENESAS
counter clear source.
external clock input edges. When channel 2 is set for phase counting mode, settings of the
CKEG1 and CKEG0 of the TCR are ignored and the phase counting mode operation takes
priority.
When TPSC2 = 0 and an internal clock source is selected, the timer counts only falling edges.
When TPSC2 = 1 and an external clock is selected, the count edge is as set by CKEG1 and
CKEG0. When the phase counting mode is selected for channel 2 (MDF bit in the timer mode
register is 1), the settings of TPSC2–TPSC0 of TCR2 are ignored and the phase counting
operation takes priority.
Initial value:
2. The timer synchro register (TSNC) set the synchronization.
Bit name:
Bit 5:
CCLR0 Description
0
1
0
1
Bit 3:
CKEG
0
0
1
—
compare match. When functioning as an input capture register, TCNT is cleared upon
input capture.
R/W:
Bit:
TCNT is not cleared (initial value)
TCNT is cleared by general register A (GRA) compare match or input capture*
TCNT is cleared by general register B (GRB) compare match or input capture*
Synchronizing clear: TCNT is cleared in synchronization with clear of other
timer counters operating in sync.*
Description
Count rising edges (initial value)
Count falling edges
Count both rising and falling edges
—
—
7
*
CCLR1
R/W
6
0
CCLR0
R/W
5
0
CKEG1 CKEG0
2
R/W
4
0
R/W
3
0
TPSC2
R/W
2
0
TPSC1
R/W
1
0
TPSC0
R/W
0
0
1
1