HD6417020SX20IV Renesas Electronics America, HD6417020SX20IV Datasheet - Page 118

• Manufacturer Part Number: HD6417020SX20IV
• Description: SH 1 CORE 32B MPU, 20MHZ/5V, 100
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SX20IV

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit 14: IOE
0
1
• Bit 13 (warp mode bit (WARP)): WARP selects warp or normal mode. 0 sets it for normal
Bit 13: WARP
0
1
• Bit 12 (RD duty (RDDTY)): RDDTY selects 35% or 50% of the T1 state as the high-level duty
Bit 12: RDDTY
0
1
• Bit 11 (byte access select (BAS)): BAS selects whether byte access control signals are WRH,
Bit 11: BAS
0
1
• Bits 10–0 (reserved): These bits always read as 0. The write value should always be 0.
8.2.2
Wait state control register 1 is a 16-bit read/write register that controls the number of states for
accessing each area and the whether wait states are used. WCR1 is initialized to H'FFFF by a
power-on reset. It is not initialized by a manual reset or by the standby mode.
98 RENESAS
mode and 1 sets it for warp mode. In warp mode, some external accesses are carried out in
parallel with internal access.
cycle ratio of signal RD. 0 sets it for 50%, 1 sets it for 35%. Only set to 1 when the operating
frequency is a minimum of 10 MHz.
WRL, and A0, or LBS, WR and HBS during word space accesses. When this bit is cleared to
0, WRH, WRL, and A0 signals are valid; when set to 1, LBS, WR, and HBS, signals are valid.
Wait State Control Register 1 (WCR1)
Description
Area 6 is external memory space (initial value)
Area 6 is an address/data multiplexed I/O area
Description
Normal mode: External and internal accesses are not simultaneously
performed (initial value)
Warp mode: External and internal accesses are simultaneously
performed
Description
RD signal high-level duty cycle is 50% of T1 state (initial value)
RD signal high-level duty cycle is 35% of T1 state
Description
WRH, WRL, and A0 enabled (initial value)
LBS, WR, and HBS enabled