HD6417020SX20IV Renesas Electronics America, HD6417020SX20IV Datasheet - Page 213

• Manufacturer Part Number: HD6417020SX20IV
• Description: SH 1 CORE 32B MPU, 20MHZ/5V, 100
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SX20IV

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

• Dual Address Mode
1. External memory and external memory transfer
2. External memory and memory-mapped external devices transfer
3. Memory-mapped external devices and memory-mapped external devices transfer
4. External memory and on-chip memory transfer
5. External memory and on-chip peripheral modules (excluding the DMAC) transfer
6. Memory-mapped external devices and on-chip memory transfer
7. Memory-mapped external devices and on-chip peripheral modules (excluding the DMAC)
8. On-chip memory and on-chip memory transfer
9. On-chip memory and on-chip peripheral modules (excluding the DMAC) transfer
10. On-chip peripheral modules (excluding the DMAC) and on-chip peripheral modules
194 RENESAS
In the dual address mode, both the transfer source and destination are accessed (selectable) by
an address. The source and destination can be located externally or internally. The source is
accessed in the read cycle and the destination in the write cycle, so the transfer is performed in
two separate bus cycles. The transfer data is temporarily stored in the DMAC. Figure 9.8
shows an example of a transfer between two external memories in which data is read from one
memory in the read cycle and written to the other memory in the following write cycle.
In the dual address mode transfers, external memory, memory-mapped external devices, on-
chip memory and on-chip peripheral modules can be mixed without restriction. Specifically,
this enables the following transfer types:
transfer
(excluding the DMAC) transfer
SuperH microcomputer
Figure 9.8 Data Flow in Dual Address Mode
DMAC
1: Read cycle
2: Write cycle
External data bus
: Data flow
2
1
External
External
memory
memory