HD6417020SX20IV Renesas Electronics America, HD6417020SX20IV Datasheet
HD6417020SX20IV
Specifications of HD6417020SX20IV
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HD6417020SX20IV Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April ...
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Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may ...
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SH7020 and SH7021 32 Hardware Manual SuperH™ RISC engine HD6437020, HD6477021, HD6437021, HD6417021 Rev.3.0 1998.09 ...
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...
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Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with ...
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The SH7020 and SH7021 are part of a new generation of reduced instruction-set computer-type (RISC) microcomputers that integrate RISC-type CPUs and the peripheral functions required for system configuration onto a single chip to achieve high-performance operations processing. They can operate ...
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Organization of This Manual Table 1 describes how this manual is organized. Figure 1 shows the relationships between the Sections within this manual. Table 1 Manual Organization Category Section Title Overview 1. Overview CPU 2. CPU Operating 3. Operating Modes ...
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Table 1 Manual Organization (cont) Category Section Title Pins 14. Pin Function Controller 15. Parallel I/O Ports Memory 16. ROM 17. RAM Power-Down 18. Power-Down States States Electrical 19. Electrical Characteristics Characteristics Abbrevi- ation Contents PFC Pin function selection I/O ...
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CPU 7. Clock pulse generator (CPG) Buses 8. Bus state controller (BC) 9. Direct memory access controller (DMAC) Memory 16. ROM 17. RAM Pins 14. Pin function controller (PFC) 15. Parallel I/O ports Manual Organization Scheme 1. Overview 3. ...
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Addresses of On-Chip Peripheral Module Registers The on-chip peripheral module registers are located in the on-chip peripheral module space (area 5: H'5000000–H'5FFFFFF), but since the actual register space is only 512 bytes, address bits A23–A9 are ignored. 32k shadow areas ...
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Section 1 Overview ............................................................................................................ 1.1 SH Microcomputer Features.............................................................................................. 1.2 Block Diagram................................................................................................................... 1.3 Pin Descriptions................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions........................................................................................................ 1.3.3 Pin Layout by Mode ............................................................................................. Section 2 CPU ...................................................................................................................... 15 2.1 Register Configuration ...................................................................................................... 15 2.1.1 General Registers ...
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Exception Processing Types and Priorities .......................................................... 47 4.1.2 Exception Processing Operation .......................................................................... 49 4.1.3 Exception Process Vector Table .......................................................................... 49 4.2 Reset .................................................................................................................................. 51 4.2.1 Reset Types .......................................................................................................... 51 4.2.2 Power-On Reset.................................................................................................... 51 4.2.3 Manual Reset........................................................................................................ 52 4.3 Address ...
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Interrupt Control Register (ICR) .......................................................................... 69 5.4 Interrupt Operation ............................................................................................................ 70 5.4.1 Interrupt Sequence................................................................................................ 70 5.4.2 Stack after Interrupt Exception Processing .......................................................... 72 5.5 Interrupt Response Time.................................................................................................... 73 5.5 Usage Notes ....................................................................................................................... 74 Section 6 User Break Controller (UBC) ...
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Wait State Control Register 1 (WCR1)................................................................ 98 8.2.3 Wait State Control Register 2 (WCR2)................................................................ 101 8.2.4 Wait State Control Register 3 (WCR3)................................................................ 103 8.2.5 DRAM Area Control Register (DCR).................................................................. 104 8.2.6 Refresh Control Register (RCR) .......................................................................... 107 8.2.7 Refresh ...
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Overview............................................................................................................................ 169 9.1.1 Features ................................................................................................................ 169 9.1.2 Block Diagram...................................................................................................... 170 9.1.3 Pin Configuration ................................................................................................. 172 9.1.4 Register Configuration ......................................................................................... 173 9.2 Register Descriptions......................................................................................................... 174 9.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) .......................................... 174 9.2.2 DMA Destination Address Registers 0-3 ...
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CPU Interface .................................................................................................................... 241 10.3.1 16-Bit Accessible Registers.................................................................................. 241 10.3.2 8-Bit Accessible Registers.................................................................................... 243 10.4 Description of Operation ................................................................................................... 244 10.4.1 Overview .............................................................................................................. 244 10.4.2 Basic Functions .................................................................................................... 245 10.4.3 Synchronizing Mode ............................................................................................ 256 10.4.4 PWM Mode .......................................................................................................... 258 ...
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Port B Data Register (PBDR)............................................................................... 307 11.2.3 Next Data Register A (NDRA) ............................................................................ 308 11.2.4 Next Data Register B (NDRB) ............................................................................. 310 11.2.5 Next Data Enable Register A (NDERA).............................................................. 311 11.2.6 Next Data Enable Register B (NDERB) .............................................................. 312 ...
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Block Diagram...................................................................................................... 342 13.1.3 Input/Output Pins.................................................................................................. 343 13.1.4 Register Configuration ......................................................................................... 343 13.2 Register Descriptions......................................................................................................... 344 13.2.1 Receive Shift Register .......................................................................................... 344 13.2.2 Receive Data Register .......................................................................................... 344 13.2.3 Transmit Shift Register ........................................................................................ 344 13.2.4 Transmit Data Register......................................................................................... 345 ...
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Socket Adapter Pin Correspondence and Memory Map ..................................... 421 16. 3 PROM Programming ......................................................................................................... 423 16.3.1 Selecting the Programming Mode........................................................................ 423 16.3.2 Write/Verify and Electrical Characteristics.......................................................... 424 16.3.3 Points to Note About Writing............................................................................... 428 16.3.4 Reliability After Writing ...................................................................................... ...
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A.2.2 Bit Rate Register (BRR)....................................................................................... 510 A.2.3 Serial Control Register (SCR).............................................................................. 510 A.2.4 Transmit Data Register (TDR) ............................................................................. 512 A.2.5 Serial Status Register (SSR)................................................................................. 512 A.2.6 Receive Data Register (RDR) .............................................................................. 514 A.2.7 Timer Start Register (TSTR)................................................................................ 515 A.2.8 Timer ...
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A.2.45 Refresh Timer Counter Register (RTCNT).......................................................... 558 A.2.46 Refresh Timer Constant Register (RTCOR) ........................................................ 559 A.2.47 Timer Control/Status Register (TCSR) ................................................................ 559 A.2.48 Timer Counter (TCNT) ........................................................................................ 561 A.2.49 Reset Control/Status Register (RSTCSR) ............................................................ 561 A.2.50 Standby Control Register (SBYCR) ...
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SuperH Microcomputer Features The SuperH microcomputer (SH7000 series new generation reduced instruction set computer (RISC) in which a Hitachi-original CPU and the peripheral functions required for system configuration are integrated onto a single chip. The CPU has ...
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Table 1.1 Features of the SH7020 and SH7021 Microcomputers Feature CPU Operating modes 2 RENESAS Description Original Hitachi architecture 32-bit internal data paths General-register machine: • Sixteen 32-bit general registers • Three 32-bit control registers • Four 32-bit system registers ...
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Table 1.1 Features of the SH7020 and SH7021 Microcomputers (cont) Feature Interrupt controller (INTC) User break controller (UBC) Clock pulse generator (CPG) Bus state controller (BSC) Description Nine external interrupt pins (NMI, IRQ0–IRQ7) Thirty internal interrupt sources Sixteen programmable priority ...
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Table 1.1 Features of the SH7032 and SH7034 Microcomputers (cont) Feature Direct memory access controller (DMAC) (4 channels) 16-bit integrated-timer pulse unit (ITU) Timing pattern controller (TPC) Watchdog timer (WDT) (1 channel) Serial communication interface (SCI) (2 channels) Can transmit ...
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Table 1.1 Features of the SH7032 and SH7034 Microcomputers (cont) Feature Description I/O ports Total of 40 I/O lines (32 input/output lines, 8 input-only lines): • Port A: 16 input/output lines (input or output can be selected for • Port ...
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...
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Block Diagram 2 RES(Vpp)* WDTOVF MD2 MD1 MD0 NMI CK EXTAL XTAL ...
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Pin Descriptions 1.3.1 Pin Arrangement AD0 1 AD1 2 AD2 AD3 5 AD4 6 AD5 7 AD6 8 AD7 9 AD8 10 AD9 11 AD10 AD11 AD12 ...
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Pin Functions Table 1.3 describes the pin functions. Table 1.3 Pin Functions Type Symbol Pin No. Power V 13, 38, CC 63, 73, 80 15, 24, SS 32, 41, 50, 59, 70, 81, 82 ...
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Table 1.3 Pin Functions (cont) Type Symbol Pin No. Operating MD2, 79–77 mode MD1, control MD0 Interrupts NMI 74 65–68, IRQ0– IRQ7 97–100 61 IRQOUT Address A21–A0 45–42, 40, bus 39, 37–33, 31–25, 23–20 Data bus AD15– 19–16, 14, AD0 ...
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Table 1.3 Pin Functions (cont) Type Symbol Pin No. Bus RAS 52 control (cont) 47 CASH 49 CASL WRH 55 WRL CS0–CS7 46–49, 51– HBS, LBS 20 DMAC DREQ0, 66, 68 DREQ1 ...
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Table 1.3 Pin Functions (cont) Type Symbol Pin No. 16-bit TOCXA4, 90, 91 integrated- TOCXB4 timer pulse TCLKA– 65, 66, unit (ITU) TCLKD 90, 91 Timing TP15– 100–93, pattern TP0 91–89, controller 87–83 (TPC) Serial TxD0, 94, 96 com- TxD1 ...
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Pin Layout by Mode Table 1.4 shows pin layout by mode Table 1.4 Pin Layout by Mode Pin No. MCU Mode 1 AD0 2 AD1 3 AD2 4 Vss 5 AD3 6 AD4 7 AD5 8 AD6 9 AD7 ...
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Table 1.3.3 Pin Layout by Mode (cont) Pin No. MCU Mode 57 PA6/RD 58 PA7/BACK PA8/BREQ 61 PA9/AH/IRQOUT 62 PA10/DPL/TIOCA1 PA11/DPH/TIOCB1 65 PA12/IRQ0/DACK0/ TCLKA 66 PA13/IRQ1/DREQ0/ TCLKLB 67 PA14/IRQ2/DACK1 68 PA15/IRQ3/DREQ1 69 ...
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Register Configuration The register set consists of sixteen 32-bit general registers, three 32-bit control registers, and four 32-bit system registers. 2.1.1 General Registers (Rn) General registers Rn consist of sixteen 32-bit registers (R0–R15). General registers are used for data ...
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GBR addressing mode to transfer data to the registers of peripheral on-chip modules. The vector base register functions as the base address of the exception processing vector area including interrupts ...
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MACL 2.1.4 Initial Values of Registers Table 2.1 lists the values of the registers after reset. Table 2.1 Initial Values of Registers Classification Register General register R0–R14 R15 (SP) Control register SR GBR ...
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Data Format in Memory Memory data formats are classified into bytes, words, and long words. Byte data can be accessed from any address, but an address error will occur if you try to access word data starting from ...
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Instruction Features 2.3.1 RISC-Type Instruction Set All instructions are RISC type. Their features are as follows: 16-Bit Fixed Length: Every instruction is 16 bits long, making program coding much more efficient. One Instruction/Cycle: Basic instructions can be executed in ...
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T bit: T bit (in the status register) is set according to the result of a comparison, and in turn is the condition (True/False) that determines if the program will branch. The T bit in the status register is ...
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Table 2.6 Absolute Address Accessing Classification CPU of SH7000 Series Absolute address MOV.L @(disp,PC), R1 MOV. B @R1, R0 ......... .DATA.L Note: The address of the immediate data is accessed by @(disp, PC). 16/32-Bit Displacement: When data is accessed by ...
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Addressing Modes Addressing modes and effective address calculation are described in table 2.8. Table 2.8 Addressing Modes and Effective Addresses Addressing Mnemonic Mode Expression Direct Rn register addressing Indirect @Rn register addressing Post-incre- @Rn + ment indirect register addressing ...
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Table 2.8 Addressing Modes and Effective Addresses (cont) Addressing Mnemonic Mode Expression Effective Addresses Calculation Indirect @(disp:4, The effective address is Rn plus a 4-bit displacement register Rn) (disp). disp is zero-extended, and remains the same addressing for a byte ...
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Table 2.8 Addressing Modes and Effective Addresses (cont) Addressing Mnemonic Mode Expression Effective Addresses Calculation PC relative @(disp:8, The effective address is the PC value plus an 8-bit addressing PC) displacement (disp). disp is zero-extended, and with dis- remains the ...
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Table 2.8 Addressing Modes and Effective Addresses (cont) Addressing Mnemonic Mode Expression Effective Addresses Calculation Immediate #imm:8 The 8-bit immediate data (imm) for the TST, AND, addressing OR, and XOR instructions are zero-extended. #imm:8 The 8-bit immediate data (imm) for ...
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Table 2.9 Instruction Formats (cont) Instruction Formats m format 15 xxxx mmmm xxxx xxxx nm format 15 xxxx nnnn xxxx mmmm md format 15 xxxx xxxx mmmm dddd nd4 format 15 xxxx xxxx dddd nnnn Note: In MAC instructions, nnnn ...
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Table 2.9 Instruction Formats (cont) Instruction Formats nmd format 15 xxxx nnnn mmmm dddd d format 15 xxxx xxxx dddd dddd d12 format 15 xxxx dddd dddd dddd nd8 format 15 xxxx nnnn dddd dddd i format 15 xxxx xxxx ...
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Instruction Set 2.4.1 Instruction Set by Classification Table 2.10 lists instructions by classification. Table 2.10 Classification of Instructions Classifi- Operation cation Types Code Data 5 MOV transfer MOVA MOVT SWAP XTRCT Arithmetic 17 ADD operations ADDC ADDV CMP/cond DIV1 ...
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Table 2.10 Classification of Instructions (cont) Classifi- Operation cation Types Code Logic oper- 6 TST ations(cont) XOR Shift 10 ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn Branch BRA BSR JMP JSR RTS System 11 ...
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Instruction codes, operation, and execution states are listed in the following format in order by classification. Table 2.11 Instruction Code Format Item Format Instruction SRC,DEST OP: Operation code OP.Sz mnemonic Instruction MSB LSB code Operation , summary (xx) M/Q/T & ...
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Table 2.12 Data Transfer Instructions Instruction MOV #imm,Rn MOV.W @(disp,PC),Rn 1001nnnndddddddd MOV.L @(disp,PC),Rn 1101nnnndddddddd MOV Rm,Rn MOV.B Rm,@Rn MOV.W Rm,@Rn MOV.L Rm,@Rn MOV.B @Rm,Rn MOV.W @Rm,Rn MOV.L @Rm,Rn MOV.B Rm,@–Rn MOV.W Rm,@–Rn MOV.L Rm,@–Rn MOV.B @Rm+,Rn MOV.W @Rm+,Rn MOV.L @Rm+,Rn ...
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Table 2.12 Data Transfer Instructions (cont) Instruction MOV.L Rm,@(R0,Rn) MOV.B @(R0,Rm),Rn MOV.W @(R0,Rm),Rn MOV.L @(R0,Rm),Rn MOV.B R0,@(disp,GBR) 11000000dddddddd MOV.W R0,@(disp,GBR) 11000001dddddddd MOV.L R0,@(disp,GBR) 11000010dddddddd MOV.B @(disp,GBR),R0 11000100dddddddd MOV.W @(disp,GBR),R0 11000101dddddddd MOV.L @(disp,GBR),R0 11000110dddddddd MOVA @(disp,PC),R0 MOVT Rn SWAP.B Rm,Rn SWAP.W ...
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Table 2.13 Arithmetic Instructions Instruction Instruction Code ADD Rm,Rn 0011nnnnmmmm1100 ADD #imm,Rn 0111nnnniiiiiiii ADDC Rm,Rn 0011nnnnmmmm1110 ADDV Rm,Rn 0011nnnnmmmm1111 CMP/EQ #imm,R0 10001000iiiiiiii CMP/EQ Rm,Rn 0011nnnnmmmm0000 CMP/HS Rm,Rn 0011nnnnmmmm0010 CMP/GE Rm,Rn 0011nnnnmmmm0011 CMP/HI Rm,Rn 0011nnnnmmmm0110 CMP/GT Rm,Rn 0011nnnnmmmm0111 CMP/PZ Rn 0100nnnn00010001 ...
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Table 2.13 Arithmetic Instructions (cont) Instruction Instruction Code EXTS.W Rm,Rn 0110nnnnmmmm1111 EXTU.B Rm,Rn 0110nnnnmmmm1100 EXTU.W Rm,Rn 0110nnnnmmmm1101 MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 MULS Rm,Rn 0010nnnnmmmm1111 MULU Rm,Rn 0010nnnnmmmm1110 NEG Rm,Rn 0110nnnnmmmm1011 NEGC Rm,Rn 0110nnnnmmmm1010 SUB Rm,Rn 0011nnnnmmmm1000 SUBC Rm,Rn 0011nnnnmmmm1010 SUBV Rm,Rn ...
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Table 2.14 Logic Operation Instructions Instruction AND Rm,Rn AND #imm,R0 AND.B #imm,@(R0,GBR) 11001101iiiiiiii (R0 + GBR) & imm NOT Rm,Rn OR Rm,Rn OR #imm,R0 #imm,@(R0,GBR) 11001111iiiiiiii (R0 + GBR) | imm OR.B TAS.B @Rn TST Rm,Rn TST #imm,R0 TST.B #imm,@(R0,GBR) ...
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Table 2.15 Shift Instructions Instruction Instruction Code ROTL Rn 0100nnnn00000100 ROTR Rn 0100nnnn00000101 ROTCL Rn 0100nnnn00100100 ROTCR Rn 0100nnnn00100101 SHAL Rn 0100nnnn00100000 SHAR Rn 0100nnnn00100001 SHLL Rn 0100nnnn00000000 SHLR Rn 0100nnnn00000001 SHLL2 Rn 0100nnnn00001000 SHLR2 Rn 0100nnnn00001001 SHLL8 Rn 0100nnnn00011000 ...
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Table 2.17 System Control Instructions Instruction Instruction Code 0000000000001000 0 CLRT 0000000000101000 0 CLRMAC 0100mmmm00001110 Rm LDC Rm,SR 0100mmmm00011110 Rm LDC Rm,GBR 0100mmmm00101110 Rm LDC Rm,VBR 0100mmmm00000111 (Rm) LDC.L @Rm+,SR 0100mmmm00010111 (Rm) LDC.L @Rm+,GBR 0100mmmm00100111 (Rm) LDC.L @Rm+,VBR 0100mmmm00001010 Rm ...
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Table 2.17 System Control Instructions (cont) Instruction Instruction Code STS.L MACH,@–Rn 0100nnnn00000010 Rn–4 STS.L MACL,@–Rn 0100nnnn00010010 Rn–4 0100nnnn00100010 Rn–4 STS.L PR,@–Rn 11000011iiiiiiii PC/SR TRAPA #imm Note: Instruction execution cycles: The execution cycles shown in the table are minimums. The actual ...
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Operation Code Map Table 2. operation code map. Table 2.18 Operation Code Map Instruction Code Fx: 0000 MSB LSBMD: 00 0000 Rn Fx 0000 0000 Rn Fx 0001 0000 Rn Fx 0010 STC 0000 Rn Fx 0011 ...
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Table 2.18 Operation Code Map (cont) Instruction Code Fx: 0000 MSB LSB MD: 00 0100 Rn Fx 0011 STC.L SR,@–Rn 0100 Rn Fx 0100 ROTL Rn 0100 Rn Fx 0101 ROTR Rn 0100 Rm Fx 0110 LDS.L @Rm+,MACH 0100 Rm ...
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Table 2.18 Operation Code Map (cont) Instruction Code Fx: 0000 MSB LSB MD: 00 1100 00MD imm/disp MOV.B R0,@ (disp:8,GBR) 1100 01MD disp MOV.B @(disp:8, GBR),R0 1100 10MD imm TST #imm:8,R0 1100 11MD imm TST.B #imm:8, @(R0,GBR) 1101 Rn disp ...
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From any state when RES = 0 and NMI = 1 Power-on reset state When an interrupt source or DMA address error occurs Bus request Bus release state Bus request generated Bus request generated Bus request cleared Sleep mode Figure ...
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On a power-on reset, all CPU internal states and on-chip peripheral module registers are initialized manual reset, all CPU internal states and on-chip peripheral module registers, with the exception of the bus state controller (BSC) and pin function ...
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Software Standby Mode: To enter the standby mode, set the standby bit SBY (in the standby control register SBYCR and execute a SLEEP instruction. In standby mode, all CPU, on-chip peripheral module and oscillator functions are halted. CPU ...
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Section 3 Operating Modes 3.1 Types of Operating Modes and Their Selection The SH7020 and SH7021 operate in one of four operating modes (modes and 7). Modes 0 and 1 differ in the bus width of memory ...
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Section 4 Exception Processing 4.1 Overview 4.1.1 Exception Processing Types and Priorities As figure 4.1 indicates, exception processing may be caused by a reset, address error, interrupt, or instruction. Exception sources are prioritized as indicated in figure 4.1. If two ...
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Reset Address error Interrupt Exception source Instruction Notes: 1. The instructions that rewrite the PC are JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, and TRAPA. 2. The delayed branch instructions are JMP, JSR. BRA. BSR, RTS, and RTE. Figure ...
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Exception Processing Operation Exception sources are detected at the times indicated in table 4.1, whereupon processing starts. Table 4.1 Exception Source Detection and Time of the Start of Processing Exception Type Reset Power-on Manual Address error Interrupt Instruction Trap ...
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Table 4.2 lists vector numbers and vector table address offsets. Table 4.3 shows how to calculate vector table addresses. Table 4.2 Exception Process Vector Table Exception Source Power-on reset Manual reset General illegal instruction (Reserved for system use) Illegal slot ...
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Table 4.3 Calculation of Exception Vector table Addresses Exception Source Reset Address error, interrupt, instructions Note: VBR: Vector base register. For vector table address offsets and vector numbers, see table 4.2. 4.2 Reset 4.2.1 Reset Types A reset is the ...
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Clears the vector base register (VBR) to H'00000000, and sets interrupt mask bits I3–I0 in the status register (SR) to H'F (1111). 4. Loads the values read from the exception vector table into PC and SP and starts program ...
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Table 4.5 Address Error Sources Bus Cycle Type Bus Master Instruction fetch CPU Data read/write CPU or DMAC Note: See section 8, Bus State Controller, for details on the on-chip peripheral module space. 4.3.2 Address Error Exception Processing When an ...
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Interrupts 4.4.1 Interrupt Sources Table 4.6 lists the types of interrupt exception processing sources (NMI, user break, IRQ, on-chip peripheral module). Table 4.6 Interrupt Sources Interrupt Requesting Pin or Module NMI NMI pin (external input) User break User break ...
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Interrupt Exception Processing When an interrupt is generated, the INTC ascertains the interrupt rankings. NMI is always accepted, but other interrupts are only accepted if their ranking is higher than the ranking set in the interrupt mask bits (I3–I0) ...
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Illegal Slot Instruction An instruction located immediately after a delayed branch instruction is called an “instruction placed in a delay slot.” undefined instruction is located in a delay slot, illegal slot instruction exception processing begins executing when ...
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Cases in Which Exceptions Are Not Accepted In some cases, address errors and interrupts that directly follow a delayed branch instruction or interrupt-disabled instruction are not accepted immediately. Table 4.9 lists these cases. When this occurs, the exception is ...
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Stack Status after Exception Processing Table 4.10 shows the stack after exception processing. Table 4.10 Stack after Exception Processing Type Stack Status Address Address of error instruction SP after instruc- tion that has finished executing SR Trap Address of ...
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Notes 4.8.1 Value of the Stack Pointer (SP) An address error occurs if the stack is accessed for exception processing when the value of the stack pointer (SP) is not a multiple of four. Therefore, a multiple of four ...
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Section 5 Interrupt Controller (INTC) 5.1 Overview The interrupt controller (INTC) determines the priority of interrupt sources and controls interrupt requests to the CPU. INTC has registers for assigning priority levels to interrupt sources. These registers handle interrupt requests according ...
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IRQOUT NMI IRQ0 IRQ1 Input IRQ2 control IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 (Interrupt request) UBC (Interrupt request) DMAC (Interrupt request) ITU (Interrupt request) SCI (Interrupt request) PRT (Interrupt request) WDT (Interrupt request) REF ICR UBC: User break controller DMAC: Direct ...
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Pin Configuration INTC pins are summarized in table 5.1. Table 5.1 INTC Pin Configuration Name Nonmaskable interrupt input pin Interrupt request input pins Interrupt request output pin 5.1.4 Registers The interrupt controller has six registers as listed in table ...
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NMI Interrupts NMI is the highest-priority interrupt (level 16) and is always accepted. Input at the NMI pin is edge-sensed. Either the rising or falling edge can be selected by setting the NMI edge select bit (NMIE) in the ...
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Interrupt Exception Vectors and Priority Rankings Table 5.3 lists the vector numbers, vector table address offsets, and interrupt priority order of the interrupt sources. Each interrupt source is allocated a different vector number and vector table address offset. The ...
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Table 5.3 Interrupt Exception Vectors and Rankings Interrupt Pri- ority Order Interrupt Source (initial value) NMI 16 User break 15 IRQ0 0–15 (0) IRQ1 0–15 (0) IRQ2 0–15 (0) IRQ3 0–15 (0) IRQ4 0–15 (0) IRQ5 0–15 (0) IRQ6 0–15 ...
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Table 5.3 Interrupt Exception Vectors and Rankings (cont) Interrupt Pri- ority Order Interrupt Source (initial value) ITU3 IMIA3 0–15 (0) IMIB3 OVI3 Reserved ITU4 IMIA4 0–15 (0) IMIB4 OVI4 Reserved SCI0 ERI0 0–15 (0) RxI0 TxI0 TEI0 SCI1 ERI1 0–15 ...
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Register Descriptions 5.3.1 Interrupt Priority Registers A–E (IPRA–IPRE) The five registers from IPRA–IPRE are 16-bit read/write registers that assign priority levels from 0–15 to the IRQ and on-chip peripheral module interrupt sources. Interrupt request sources are mapped onto IPRA–IPRE ...
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Interrupt Control Register (ICR) ICR is a 16-bit register that sets the input detection mode of the external interrupt input pins NMI and IRQ0–IRQ7 and indicates the input signal level to the NMI pin. A reset initializes ICR but ...
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Interrupt Operation 5.4.1 Interrupt Sequence The sequence of interrupt operations will be explained below. Figure 5 flowchart of the operations up to acceptance of the interrupt. 1. The interrupt request sources send interrupt request signals to the ...
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Conditions" is performed. Program execution state No Interrupt? Yes No NMI? Yes User break? Yes Yes *1 IRQOUT low Pushes SR onto stack Pushes PC onto stack Copies level of accep- tance from ...
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Stack after Interrupt Exception Processing Figure 5.3 shows the stack after interrupt exception processing. Address 4n–8 4n–6 4n–4 4n–2 4n Notes: 1. Bus width is 16 bits stores the top address of the next instruction (return instruction) ...
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Interrupt Response Time Table 5.5 indicates the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception processing starts and fetching of the first instruction of the interrupt service routine begins. ...
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IRQ Instruction (instruction replaced by interrupt exception handling) Overrun fetch Interrupt service routine— first instruction IRQOUT When m3, the interrupt response time is 11 cycles. F (Instruction fetch) D (Instruction decoding) E (Instruction execution) M (Memory ...
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Section 6 User Break Controller (UBC) 6.1 Overview The user break controller (UBC) simplifies the debugging of user programs. Break conditions are set in the UBC and a user break interrupt request is sent to the CPU in response to ...
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Module bus BBR BAMRH BAMRL Break condition comparator User break interrupt generating circuit UBC BARH, BARL: Break address registers H and L BAMRH, BAMRL: Break address mask registers H and L BBR: Break bus cycle register Figure 6.1 Block Diagram ...
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Table 6.1 User Break Controller Registers Name Break address register high Break address register low Break address mask register high Break address mask register low Break bus cycle register Note: Only the values of bits A27–A24 and A8–A0 are valid; ...
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BARL: Break address register L. Bit: 15 Bit name: BA15 Initial value: 0 R/W: R/W Bit: 7 Bit name: BA7 Initial value: 0 R/W: R/W • BARL Bits 15–0 (break address 15–0 (BA15–BA0)): BA15–BA0 store the lower bit values (bits ...
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BAMRL: Break address mask register L. Bit: 15 Bit name: BAM15 Initial value: 0 R/W: R/W Bit: 7 Bit name: BAM7 Initial value: 0 R/W: R/W • BAMRL bits 15–0 (break address mask 15–0 (BAM15–BAM0)): BAM15–BAM0 specify whether bits BA15–BA0 ...
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Bit: 15 Bit name: — Initial value: 0 R/W: — Bit: 7 Bit name: CD1 Initial value: 0 R/W: R/W • Bits 15–8 (reserved): These bits always read as 0. The write value should always be 0. • Bits 7 ...
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Bits 3 and 2 (read/write select (RW1, RW0)): RW1, RW0 select whether to break on read and/or write access cycles. Bit 3: RW1 Bit 2: RW0 • Bits 1 and 0 (operand size ...
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When receiving the user break interrupt request, the interrupt controller checks its priority level. The user break interrupt has priority level 15 accepted only if the interrupt mask level in bits I3–I0 in the status register ...
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BARH/BARL Internal address bits 31–0 CD1 CD0 CPU cycle DMA cycle ID1 ID0 Instruction fetch Data access RW1 RW0 Read cycle Write cycle SZ1 SZ0 Byte size Word size Long word size Figure 6.2 Break Condition Logic BAMRH/BAMRL 32 32 ...
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Break on Instruction Fetch Cycles to On-Chip Memory On-chip memory (on-chip ROM and RAM) is always accessed 32 bits each bus cycle. Two instructionsare therefore fetched in a bus cycle from on-chip memory . Although only a single bus ...
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Register settings: BARH = H'0003, BARL = H'0147, BBR = H'0054 Conditions set: Address = H'00030147, Bus cycle = CPU, instruction fetch, read (operand size not included in conditions) No user break interrupt occurs, because instructions are always fetched ...
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Notes 6.5.1 On-Chip Memory Instruction Fetch Two instructions are simultaneously fetched from on-chip memory break condition is set on the second of these two instructions but the contents of the UBC break condition registers are changed so ...
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Instruction Fetch Break If a break is attempted at the task A return destination instruction fetch, task B is activated before the UBC interrupt by interrupt B generated during task A processing, and the UBC interrupt is handled after ...
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Section 7 Clock Pulse Generator (CPG) 7.1 Overview The SuperH microcomputer has a built-in clock pulse generator (CPG) that supplies the LSI and external devices with a clock pulse. The CPG makes the LSI run at the oscillation frequency of ...
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IC– Figure 7.2 Connection of the Crystal Resonator (Example) Table 7.1 Damping Resistance Frequency [MHz Crystal Resonator: Figure 7.3 shows an equivalent circuit of the crystal resonator. Use ...
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External clock input Figure 7.4 External Clock Input Method VIH 1 VIL t EXr Table 7.3 Input Clock Specifications 5 V Specifications (fmax = 20 MHz –V ) Max = 5 EXr (1/2 ...
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Figure 7.6 Precaution on Oscillator Circuit Board Design Duty cycle correction circuit: Duty cycle corrections are conducted for an input clock over 5 MHz. Duty cycles may not be corrected if under 5 MHz, but AC characteristics for the high-level ...
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Section 8 Bus State Controller (BSC) 8.1 Overview The bus state controller (BSC) divides address space and outputs control signals for all kinds of memory and peripheral LSIs. BSC functions enable the LSI to link directly with DRAM, SRAM, ROM, ...
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WAIT RD WRH, WRL HBS, LBS AH CS7 to CS0 CASH, CASL RAS CMI interrupt request DPH, DPL PEI interrupt request Interrupt controller WCR: Wait state control register BCR: Bus control register DCR: DRAM area control register RCR: Refresh control ...
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Pin Configuration Table 8.1 shows the BSC pin configuration. Table 8.1 Pin Configuration Name Abbreviation Chip select 7–0 CS7–CS0 Read RD High write WRH Low write WRL 1 Write WR* 2 High byte strobe HBS* 3 Low byte strobe ...
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Table 8.2 Register Configuration Name Bus control register Wait state control register 1 Wait state control register 2 Wait state control register 3 DRAM area control register Parity control register Refresh control register Refresh timer control/status register Refresh timer counter ...
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On-chip ROM space in area 0: Always 32 bits • External memory space in area 0: 8 bits when MD0 pin bits when the pin is 1 • On-chip peripheral module space in area 5: 8 ...
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Bit 14: IOE Description 0 Area 6 is external memory space (initial value) 1 Area address/data multiplexed I/O area • Bit 13 (warp mode bit (WARP)): WARP selects warp or normal mode. 0 sets it for normal ...
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Bit: 15 Bit name: RW7 Initial value: 1 R/W: R/W Bit: 7 Bit name: — Initial value: 1 R/W: — • Bits 15–8 (wait state control during read (RW7–RW0)): RW7–RW0 determine the number of states in read cycles for each ...
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Table 8.3 Read Cycle State Description WAIT Bits 15–8: Pin Input External Memory RW7–RW0 Signal Space 0 Not • Areas 1, 3–5,7: 1 sampled state, fixed during Areas state read + long wait state 1 cycle* ...
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Wait State Control Register 2 (WCR2) Wait state control register 16-bit read/write register that controls the number of states for accessing each area with a DMA single address mode transfer and whether wait states are used. ...
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Table 8.4 Single-Mode DMA Memory Read Cycle States (External Memory Space) Description Bits 15–8: WAIT Pin Input DRW7–DRW0 Signal 0 Not sampled during single-mode DMA memory read cycle* 1 Sampled during single-mode DMA memory read cycle (initial value) Note: Sampled ...
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Table 8.5 Single-Mode DMA Memory Write Cycle States (External Memory Space) Description Bits 15–8: WAIT Pin Input DWW7–DWW0 Signal 0 Not sampled during single-mode DMA memory write cycle* 1 Sampled during single-mode DMA memory write cycle (initial value) Note: Sampled ...
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Bit 15: WPU Description 0 WAIT pin is not pulled up 1 WAIT pin is pulled up (initial value) • Bits 14 and 13 (long wait insertion in areas 0 and 2, bits 1, 0 (A02LW1 and A02LW0)): A02LW1 and ...
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Bit: 15 Bit name: CW2 Initial value: 0 R/W: R/W Bit: 7 Bit name: — Initial value: 0 R/W: — • Bit 15 (dual-CAS or dual-WE select bit (CW2)): When accessing a 16-bit bus width space, CW2 selects the dual-CAS ...
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Bit 12 (burst operation enable (BE)): BE selects whether or not to perform burst operation, a high speed page mode. When burst operation is not selected (0), the row address is not compared but instead is transferred to the ...
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Bit 9: Bit 8: Row Address Shift MXC1 MXC0 (MXE = bits (initial value bits bits 1 Reserved Bits 7–0 (reserved): These bits always read as 0. The write value should ...
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Bit 7: RFSHE Description 0 Refresh control disabled. RTCNT can be used as an 8-bit interval timer. (initial value) 1 Refresh control enabled • Bit 6 (refresh mode (RMODE)): When DRAM refresh control is selected (RFSHE = 1), RMODE selects ...
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Bit: 15 Bit name: — Initial value: 0 R/W: — Bit: 7 Bit name: CMF Initial value: 0 R/W: R/W • Bits 15–8 (reserved): These bits always read as 0. • Bit 7 (compare match flag (CMF)): CMF is a ...
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Bit 5: CKS2 Bit 4: CKS1 • Bits 2–0 (reserved): These bits always read as 0. The write value should always be 0. 8.2.8 Refresh Timer Counter (RTCNT) The refresh timer counter (RTCNT) is ...
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Bit Bit name: — — Initial value R/W: — — Bit Bit name: Initial value R/W: R/W R — — — — — — ...
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Refresh Time Constant Register (RTCOR) The refresh time constant register (RTCOR 16-bit read/write register that sets the compare match cycle used with RTCNT. The values in RTCOR and RTCNT are constantly compared. When they match, the compare-match ...
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Bit: 15 Bit name: PEF Initial value: 0 R/W: R/W Bit: 7 Bit name: — Initial value: 0 R/W: — • Bit 15 (parity error flag (PEF)): When a parity check is done, PEF indicates whether a parity error has ...
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Bit 12: PCHK1 Bit 11: PCHK0 • Bits 10–0 (reserved): These bits always read as 0. The write value should always be 0. 8.2.11 Notes on Register Access RCR, RTCSR, RTCNT, and RTCOR differ ...
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Address Space Subdivision 8.3.1 Address Spaces and Areas Figure 8.3 shows the address format used in this LSI. A31–A28 A27 A26–A24 Basic bus width selection: Not output externally, but used for basic bus width selection When 0, (H'0000000–H'7FFFFFF), the ...
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Table 8.6 How Space is Divided Area Address 0 H'0000000 – H'0FFFFFF On-chip ROM* 1 H'1000000 – H'1FFFFFF External memory 2 H'2000000 – H'2FFFFFF External memory 3 H'3000000 – H'3FFFFFF External memory 4 H'4000000 – H'4FFFFFF External memory 5 H'5000000 ...
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As figure 8.4 shows, specific spaces such as DRAM space and address/data multiplexed I/O space are allocated to the 8 areas. Each of the spaces is equipped with the necessary interfaces. The control signals needed by DRAM and peripheral LSIs ...
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Table 8.7 A26–A24 Bits and Chip Select Signals Address A26 A25 A24 The chip select signal is output only for external accesses. When accessing the on-chip ...
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Logical address space H'B000000 H'3000000 H'B3FFFFF (A23, A22 = 00) H'B400000 H'33FFFFF H'3400000 H'B7FFFFF (A23, A22 = 01) H'B800000 H'37FFFFF H'3800000 H'BBFFFFF (A23, A22 = 10) H'BC00000 H'3BFFFFF H'3C00000 H'BFFFFFF (A23, A22 = 11) H'3FFFFFF 16-bit space a. Shadow allocation ...
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Area Description Area 0: Area 0 is the area where addresses A26–A24 are 000 and its address range is H'0000000– H'0FFFFFF and H'8000000–H'8FFFFFF. Figure 8 memory map of area 0. Area 0 can be set for use ...
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Logical address space H'8000000 H'8003FFF(SH7020) H'0000000 H'8007FFF(SH7021) Shadow H'0003FFF H'8004000(SH7020) Shadow (SH7020) H'8008000(SH7021) H'0007FFF Shadow (SH7021) H'004000 (SH7020) H'0008000 (SH7021) H'8FFC000 Shadow (SH7020) H'8FF8000 Shadow H'0FFC000 (SH7021) (SH7020) Shadow H'0FF8000 (SH7021) H'0FFFFFF 32-bit space 32-bit space MD2–MD0 = 010 Note: ...
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A23–A0 are multiplexed and output from pins A15–A0 maximum 16-Mbyte space can be used. When DRAM space is accessed, the CS1 signal is not valid and the pin ...
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Areas 2–4 are always used as external memory space. The bus width is 8 bits when the A27 bit is 0 and 16 bits when A23 and A22 bits are not output and the shadow is in ...
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Area 5: Area 5 is the area where addresses A26–A24 are 101 and its address range is H'5000000– H'5FFFFFF and H'D000000–H'DFFFFFF. Figure 8 memory map of area 5. Area 5 is allocated to on-chip peripheral module space when ...
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In area 6, the space when A27 allocated to address/data multiplexed I/O space when the multiplexed I/O enable bit (IOE) of the bus control register (BCR and external memory space when the IOE bit is ...
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Logical address space H'6000000 Shadow H'63FFFFF H'6400000 Shadow H'67FFFFF H'6800000 Shadow H'6BFFFFF H'6C00000 Shadow H'6FFFFFF 8 or 16-bit space Area 7: Area 7 is the area where addresses A26–A24 are 111 and its address range is H'7000000– H'7FFFFFF and H'F000000–H'FFFFFFF. ...
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Logical address space H'7000000 Shadow H'73FFFFF H'7400000 Shadow H'77FFFFF H'7800000 (4 Mbytes) • Valid Shadow H'7BFFFFF H'7C00000 • CS7 valid Shadow H'7FFFFFF 8-bit space Figure 8 10 Memory Map of Area 7 H'F000000 H'F0003FF Actual space External memory space addresses ...
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Accessing External Memory Space In external memory space, strobe signal is output based on the assumption of a directly connected SRAM. The external memory space is allocated to the following areas: • Area 0 (when MD2–MD0 are 000 or ...
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CK A21–A0 CSn RD Read AD15–AD0 WRH, WRL Write AD15–AD0 Figure 8.12 Basic Timing of External Memory Space Access (2-state read timing) High-level duties of 35% and 50% can be selected for the RD signal using the RD duty bit ...
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Table 8.8 Number of States and Number of Wait States in the Access Cycles to External Memory Spaces CPU read cycle, DMAC dual mode read cycle, DMAC single mode read/write cycle Corresponding Bits in Area WCR1 and WCR2 = 0 ...
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CK A21–A0 CSn RD Read AD15–AD0 WRH, WRL Write AD15–AD0 WAIT Figure 8.13 Wait State Timing for External Memory Space Access (2 states plus wait states Areas 0, 2 and 6 have long wait functions. When the corresponding bits in ...
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CK A21–A0 CSn RD Read AD15–AD0 WRH, WRL Write AD15–AD0 WAIT Figure 8.14 Wait State Timing for External Memory Space Access (1 state plus long wait state (when set to insert 3 states) plus wait states from WAIT signal) For ...
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Byte Access Control The upper byte and lower byte control signals when 16-bit bus width space is being accessed can be selected from (WRH, WRL, A0) or (WR, HBS, LBS). When the byte access select bit (BAS) of the ...
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DRAM Interface Operation When the DRAM enable bit (DRAME) of the BCR is set to 1, area 1 becomes DRAM space and the DRAM interface function is available, which permits direct connection of this LSI to DRAMs. 8.5.1 DRAM ...
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Table 8.9 Relationship between Multiplex Shift Count Bits (MXC1, MXC0) and Address Multiplexing Shift Amount 8 bits Output Row Output Pin Address A21 A20 A19 Undefined A18 Value A17 A16 A15 A23 A14 A22 A13 A21 A12 A20 A11 A19 ...
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RAS = Low level Internal address A23 Address pin CAS = Low level A23 A22 A21 Internal address Address pin Figure 8.16 Address Multiplexing States (8-bit shift) 8.5.2 Basic Timing There are two types of DRAM accesses: short pitch and ...
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CK A21–A0 RAS CAS WRH, WRL Read AD15–AD0 WRH, WRL Write AD15–AD0 Figure 8.17 Short Pitch Access Timing Row address CDTY = Column address CDTY = 0 RENESAS 137 ...
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CK A21–A0 RAS CAS WRH, WRL Read AD15–AD0 WRH, WRL Write AD15–AD0 Figure 8.18 Long Pitch Access Timing 8.5.3 Wait State Control Precharge State Control: When the microprocessor clock frequency is raised and the cycle period shortened, 1 cycle may ...
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A21–A0 RAS CAS Figure 8.19 Precharge Timing (Long Pitch) Control of Insertion of Wait States Using the WAIT Pin Input Signal: The number of wait states inserted into the DRAM access cycle can be controlled by ...
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When the RW1 bit is set to 1, the number of wait states selected by CBR refresh wait state insertion bits 1 and 0 (RLW1, RLW0) of the refresh control register (RCR) are inserted into the CAS-before-RAS refresh cycle. 8.5.4 ...
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CK A21–A0 RAS CASH Byte control CASL WRH WRL CK A21–A0 RAS CASH CASL WRH Byte control WRL Figure 8.21 Byte Access Control Timing for DRAM Access (Upper Byte Write Cycle, Short Row address High level ...
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DRAM Burst Mode In addition to the normal mode of DRAM access, in which row addresses are output at every access and data then accessed (full access), the DRAM also has a high-speed page mode for use when continuously ...
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Short Pitch High-Speed Page Mode and Long Pitch High-Speed Page Mode: When burst operation is selected by setting the DCR’s BE bit to 1, the short pitch high-speed page mode or long pitch high-speed page mode can be selected by ...
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A21– A0 Row address RAS CAS WR AD15– A0 Note: Access A and B are examples of 32-bit data accesses in their respective 16-bit bus width spaces. Figure 8.24 Short Pitch High-Speed Page Mode (Write ...
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Access A (read A21– A0 Row address RAS CAS WR AD15– AD0 Note: Access A and B are examples of 32-bit data accesses in their respective 16-bit bus width spaces. Figure 8.25 Short Pitch High-Speed Page ...
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CK A21–AD0 RAS CAS WR Read AD15–AD0 WR Write AD15–AD0 Figure 8.26 Long Pitch High-Speed Page Mode (Read/Write Cycle) RAS Down Mode and RAS Up Mode: Sometimes access to another area can occur between accesses to the DRAM even though ...
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DRAM access A21– A0 Row address RAS CAS WR AD15– AD0 RAS Up Mode: When the RASD bit is cleared to 0, the RAS signal reverts to high whenever a • DRAM access pauses for ...
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DRAM access address 1 A21– A0 Row address RAS CAS AD15– AD0 8.5.6 Refresh Control The BSC has a function for controlling DRAM refreshing. By setting the refresh mode bit (RMODE) in the refresh control ...
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RTCNT again matches the RTCOR value, the initial refresh interval will be rather long thus advisable to set the RTCOR cycle prior to setting the CKS2– CKS0 bits and start it ...
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CAS and RAS signals are output as shown in figure 8.31. See section 20.3.3, Bus Timing, for details. The DRAM self-refresh mode is cleared when the RMODE bit in the RCR is cleared to ...
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Table 8.10 Refresh and Bus Cycle Contention External Memory Space, Multiplexed I/O Space Type of Refresh Read Cycle Write Cycle Read Cycle Write Cycle Peripheral Access CAS-before- Yes RAS refresh Self-refresh Yes Yes: Can be executed in parallel No: Cannot ...
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Basic Timing When the multiplexed I/O enable bit (IOE) of the BCR is set to 1, the area 6 space with address bit A27 as 0 (H'6000000–H'6FFFFFF) becomes an address/data multiplexed I/O space that, when accessed, multiplexes addresses and ...
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Wait State Control When the address/data multiplexed I/O space is accessed, the WAIT pin input signal is sampled and a wait state inserted whenever a low level is detected, regardless of the setting of the WCR. Figure 8.33 shows ...
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Parity Check and Generation The BSC can check and generate parity for data input and output to or from in the DRAM space of area 1 and the external memory space of area 2. To check and generate parity, ...
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CK A21– A0 External CSn space write WR AD15– AD0 External space Internal address Internal On-chip write peri- strobe pheral module Internal write data bus Internal On-chip read peri- strobe pheral module Internal read data bus Figure 8.34 Warp Mode ...
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Table 8.11 Bus Cycle States when Accessing Address Spaces Corresponding Bits in WCR1 Address Space and WCR2 = 0 External memory (areas 1 state fixed; WAIT signal ignored 2 states + wait states from WAIT 1, 3–5, 7) External memory ...
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For details on bus cycles when external spaces are accessed, see section 8.4, External Memory Space Access, section 8.5, DRAM Space Access, and section 8.6, Address/Data Multiplexed I/O Space Access. Accesses of on-chip spaces are as follows: On-chip peripheral module ...
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SuperH BREQ received Strobe pin: High-level output Address, data, strobe pin: High impedance Bus release response Bus released 8.10.1 The Operation of Bus Arbitration This LSI has the bus arbitration function which can give bus ownership to an external device ...
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BREQ BACK Figure 8.36 BACK Operation by Refresh Demand (1) If BACK has not gone low after waiting for the maximum number of states* before the SuperH releases the bus, return BREQ to the high level. BREQ BACK Refresh request ...
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Countermeasure against a spike on the BACK signal The following describes the countermeasure against a spike on the BACK signal: a. When BREQ is input to release the bus of the LSI, make sure that conflicts with a refresh ...
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BACK 8.11 Usage Notes 8.11.1 Usage Notes on Manual Reset Condition: When DRAM (long-pitch mode) is used and manual reset is performed. The low width of RAS output may be shorter than usual in rese + (2.5tcyc 1.5tcyc), causing the ...
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CK RES A0 to A21 RAS CAS WR AD0 to AD15 Figure 8.38 Long - pitch Mode Write (1) RES latch timing CK RES A0 to A21 RAS CAS WR AD0 to AD15 Figure 8.39 Long - pitch Mode Write ...
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RES latch CK RES A0 to A21 RAS CAS RD Figure 8.40 Long - pitch Mode Read (1) RES latch timing CK RES A0 to A21 RAS CAS RD Figure 8.41 Long - pitch Mode Read (2) For the signal ...
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The countermeasures are not required when DRAM data is initialized or loaded again after manual reset. 8.11.2 Usage Notes on Parity Data Pins DPH and DPL The following specifies the setup time tDS of the parity dada DPH and DPL ...
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BREQ is sampled one state before the bus cycle. If BREQ is input without satisfying tBRQS, the bus is released after executing cycle B following the end of bus cycle A, as shown in figure 8.43. The maximum number of ...
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Figure 8.45 TAS Instruction Read Cycle and Write Cycle (c) Refresh cycle + bus cycle The bus is never released during a refresh cycle and the following bus cycle ((a) or (b) above)) (figure 8.46). Figure 8.46 Refresh Cycle and ...
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Bus release procedure The bus release procedure is shown in figure 8.47. Figure 8.47 shows the case where BREQ is input one state before the break between bus cycles so that tBRQS is satisfied. In the SH7020 and SH7021, ...
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Section 9 Direct Memory Access Controller (DMAC) 9.1 Overview The SuperH microprocomputer chip includes a four-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high speed transfers between external devices that ...
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Two on-chip peripheral modules (excluding DMAC) • Transfer requests External request (From DREQ pins (channels 0 and 1 only). DREQ can be detected either by edge or by level) Requests from on-chip peripheral modules (serial communications interface (SCI), and 16- ...
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On-chip ROM On-chip RAM On-chip peripheral module DREQ0, DREQ1 ITU SCI DACK0, DACK1 DEIn External ROM External RAM External device (memory mapped) External device (with acknowledge) Bus controller DMAOR: DMA operation register SARn: DMA source address register DARn: DMA destination ...
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Pin Configuration Table 9.1 shows the DMAC pins. Table 9.1 Pin Configuration Channel Name 0 DMA transfer request DMA transfer request acknowledge 1 DMA transfer request DMA transfer request acknowledge 172 RENESAS Symbol I/O Function I DMA transfer request ...
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Register Configuration Table 9.2 summarizes the DMAC registers. DMAC has a total of 17 registers. Each channel has four control registers. One other control register is shared by all channels Table 9.2 DMAC Registers Chan- nel Name 0 DMA ...
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Register Descriptions 9.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) DMA source address registers 0–3 (SAR0–SAR3) are 32-bit read/write registers that specify the source address of a DMA transfer. During a DMA transfer, these registers indicate the next source address ...
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DMA Transfer Count Registers 0–3 (TCR0–TCR3) DMA transfer count registers 0-3 (TCR0–TCR3) are 16-bit read/write registers that specify the DMA transfer count (bytes or words). The number of transfers is 1 when the setting is H'0001, 65535 when the ...
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Bits 15 and 14 (destination address mode bits 1, 0 (DM1 and DM0)): DM1 and DM0 select whether the DMA destination address is incremented, decremented, or left fixed (in the single address mode, DM1 and DM0 are ignored when ...
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Bit 11: Bit 10: Bit 9: Bit 8: RS3 RS2 RS1 RS0 ...
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Bit 7 (acknowledge mode bit (AM)): In the dual address mode, AM selects whether the DACK signal is output during the data read cycle or write cycle. This bit is valid only in channels 0 and 1. The AM ...
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Bit 3 (transfer size bit (TS)): TS selects the transfer unit size. If the on-chip peripheral module that is the source or destination of the transfer can only be accessed in bytes, byte must be selected in this bit. ...
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Bit 0 (DMA enable bit (DE)): DE enables or disables DMA transfers. In the auto-request mode, the transfer starts when this bit or the DME bit of the DMAOR is set to 1. The TE bit and the NMIF ...
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Bits 9 and 8 (priority mode bits 1 and 0 (PR1 and PR0)): PR1 and PR0 select the priority level between channels when there are transfer requests for multiple channels simultaneously. Bit 9: PR1 Bit 8: PR0 0 0 ...