MC68HC16Z1CAG25 Freescale Semiconductor, MC68HC16Z1CAG25 Datasheet - Page 71

• Manufacturer Part Number: MC68HC16Z1CAG25
• Description: IC MCU 16BIT 25MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CAG25

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Cpu Family: HC16
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: SCI/SPI/UART
• Program Memory Size: Not Required
• Total Internal Ram Size: 1KB
• # I/os (max): 16
• Number Of Timers - General Purpose: 11
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Controller Family/series: 68HC16
• No. Of I/o's: 16
• Ram Memory Size: 1KB
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Processor Series: HC16Z
• Core: CPU16
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 11
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

4.6.8 Use of CPU16 Indexed Mode to Replace M68HC11 Direct Mode
4.7 Instruction Set
4.7.1 Instruction Set Summary
M68HC16 Z SERIES
USER’S MANUAL
In M68HC11 systems, the direct addressing mode can be used to perform rapid ac-
cesses to RAM or I/O mapped from $0000 to $00FF. The CPU16 uses the first 512
bytes of bank 0 for exception vectors. To provide an enhanced replacement for the
M68HC11’s direct addressing mode, the ZK field and index register Z have been as-
signed reset initialization vectors. By resetting the ZK field to a chosen page and using
indexed mode addressing, a programmer can access useful data structures anywhere
in the address map.
The CPU16 instruction set is based on the M68HC11 instruction set, but the opcode
map has been rearranged to maximize performance with a 16-bit data bus. Most
M68HC11 code can run on the CPU16 following reassembly. The user must take into
account changed instruction times, the interrupt mask, and the changed interrupt stack
frame (refer to Transporting M68HC11 Code to M68HC16 Devices ,Freescale Pro-
gramming Note M68HC16PN01/D, for more information).
Table 4-2
Reference Manual (CPU16RM/AD) for detailed information about each instruction, as-
sembler syntax, and condition code evaluation.
nomenclature.
is a quick reference to the entire CPU16 instruction set. Refer to the CPU16
Freescale Semiconductor, Inc.
For More Information On This Product,
CENTRAL PROCESSOR UNIT
Go to: www.freescale.com
Table 4-3
provides a key to the table
4-11