MC68HC16Z1CAG25 Freescale Semiconductor, MC68HC16Z1CAG25 Datasheet - Page 163
![IC MCU 16BIT 25MHZ 144-LQFP](/photos/6/76/67683/375-144-tqfp_sml.jpg)
MC68HC16Z1CAG25
Manufacturer Part Number
MC68HC16Z1CAG25
Description
IC MCU 16BIT 25MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HC16r
Datasheet
1.MC68HC16Z1VEH16.pdf
(500 pages)
Specifications of MC68HC16Z1CAG25
Core Processor
CPU16
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Cpu Family
HC16
Device Core Size
16b
Frequency (max)
25MHz
Interface Type
SCI/SPI/UART
Program Memory Size
Not Required
Total Internal Ram Size
1KB
# I/os (max)
16
Number Of Timers - General Purpose
11
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Controller Family/series
68HC16
No. Of I/o's
16
Ram Memory Size
1KB
Cpu Speed
25MHz
No. Of Timers
2
Embedded Interface Type
QSPI, SCI
Rohs Compliant
Yes
Processor Series
HC16Z
Core
CPU16
Data Bus Width
16 bit
Data Ram Size
1 KB
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
16
Number Of Timers
11
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC16Z1CAG25
Manufacturer:
FREESCAL
Quantity:
455
Company:
Part Number:
MC68HC16Z1CAG25
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 163 of 500
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5.7.9 Reset Processing Summary
5.7.10 Reset Status Register
M68HC16 Z SERIES
USER’S MANUAL
To prevent write cycles in progress from being corrupted, a reset is recognized at the
end of a bus cycle, and not at an instruction boundary. Any processing in progress at
the time a reset occurs is aborted. After SIM reset control logic has synchronized an
internal or external reset request, the MSTRST signal is asserted.
The following events take place when MSTRST is asserted.
The following events take place when MSTRST is negated after assertion.
The reset status register (RSR) contains a bit for each reset source in the MCU. When
a reset occurs, a bit corresponding to the reset type is set. When multiple causes of
reset occur at the same time, more than one bit in RSR may be set. The reset status
register is updated by the reset control logic when the RESET signal is released. Refer
to
APPENDIX D REGISTER
A. Instruction execution is aborted.
B. The condition code register is initialized.
C. The K register is cleared.
A. The CPU16 samples the BKPT input.
B. The CPU16 fetches RESET vectors in the following order:
C. The CPU16 begins fetching instructions pointed to by the initial PK : PC.
1. The IP field is set to $7, disabling all interrupts below priority 7.
2. The S bit is set, disabling LPSTOP mode.
3. The SM bit is cleared, disabling MAC saturation mode.
1. Initial ZK, SK, and PK extension field values
2. Initial PC
3. Initial SP
4. Initial IZ value
Vectors can be fetched from internal RAM or from external ROM enabled by
the CSBOOT signal.
When TSC assertion takes effect, internal signals are forced to val-
ues that can cause inadvertent mode selection. Once the output driv-
ers change state, the MCU must be powered down and restarted
before normal operation can resume.
All CCR bits that are not initialized are not affected by reset. Howev-
er, out of power-on reset, these bits are indeterminate.
Freescale Semiconductor, Inc.
For More Information On This Product,
SYSTEM INTEGRATION MODULE
SUMMARY.
Go to: www.freescale.com
NOTE
NOTE
5-57
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