MC68HC16Z1CAG25 Freescale Semiconductor, MC68HC16Z1CAG25 Datasheet - Page 161
![IC MCU 16BIT 25MHZ 144-LQFP](/photos/6/76/67683/375-144-tqfp_sml.jpg)
MC68HC16Z1CAG25
Manufacturer Part Number
MC68HC16Z1CAG25
Description
IC MCU 16BIT 25MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HC16r
Datasheet
1.MC68HC16Z1VEH16.pdf
(500 pages)
Specifications of MC68HC16Z1CAG25
Core Processor
CPU16
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Cpu Family
HC16
Device Core Size
16b
Frequency (max)
25MHz
Interface Type
SCI/SPI/UART
Program Memory Size
Not Required
Total Internal Ram Size
1KB
# I/os (max)
16
Number Of Timers - General Purpose
11
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Controller Family/series
68HC16
No. Of I/o's
16
Ram Memory Size
1KB
Cpu Speed
25MHz
No. Of Timers
2
Embedded Interface Type
QSPI, SCI
Rohs Compliant
Yes
Processor Series
HC16Z
Core
CPU16
Data Bus Width
16 bit
Data Ram Size
1 KB
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
16
Number Of Timers
11
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC16Z1CAG25
Manufacturer:
FREESCAL
Quantity:
455
Company:
Part Number:
MC68HC16Z1CAG25
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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5.7.6 Reset Timing
5.7.7 Power-On Reset
M68HC16 Z SERIES
USER’S MANUAL
The RESET input must be asserted for a specified minimum period for reset to occur.
External RESET assertion can be delayed internally for a period equal to the longest
bus cycle time (or the bus monitor time-out period) in order to protect write cycles from
being aborted by reset. While RESET is asserted, SIM pins are either in an inactive,
high-impedance state or are driven to their inactive states.
When an external device asserts RESET for the proper period, reset control logic
clocks the signal into an internal latch. The control logic drives the RESET pin low for
an additional 512 CLKOUT cycles after it detects that the RESET signal is no longer
being externally driven to guarantee this length of reset to the entire system.
If an internal source asserts a reset signal, the reset control logic asserts the RESET
pin for a minimum of 512 cycles. If the reset signal is still asserted at the end of 512
cycles, the control logic continues to assert the RESET pin until the internal reset sig-
nal is negated.
After 512 cycles have elapsed, the RESET pin goes to an inactive, high-impedance
state for ten cycles. At the end of this 10-cycle period, the RESET input is tested.
When the input is at logic level one, reset exception processing begins. If, however,
the RESET input is at logic level zero, reset control logic drives the pin low for another
512 cycles. At the end of this period, the pin again goes to high-impedance state for
ten cycles, then it is tested again. The process repeats until external RESET is
released.
When the SIM clock synthesizer is used to generate system clocks, power-on reset
involves special circumstances related to application of the system and the clock syn-
thesizer power. Regardless of clock source, voltage must be applied to clock synthe-
sizer power input pin V
assumes that V
start-up time. When V
cific crystal parameters and by oscillator circuit design. V
pin state during reset. Refer to
voltage and timing specifications.
During power-on reset, an internal circuit in the SIM drives the IMB internal (MSTRST)
and external (EXTRST) reset lines. The power-on reset circuit releases the internal re-
set line as V
ized to the values shown in
voltage, the clock synthesizer VCO begins operation. Clock frequency ramps up to
specified limp mode frequency (f
the clock synthesizer PLL locks and 512 CLKOUT cycles elapse.
V
V
DDSYN
DDSYN
DD
ramps up to the minimum operating voltage, and SIM pins are initial-
DDSYN
only will cause errant behavior of the MCU.
and all V
Freescale Semiconductor, Inc.
For More Information On This Product,
DDSYN
is applied before and during reset, which minimizes crystal
DDSYN
SYSTEM INTEGRATION MODULE
Table
is applied at power-on, start-up time is affected by spe-
DD
Go to: www.freescale.com
APPENDIX A ELECTRICAL CHARACTERISTICS
limp
for the MCU to operate. The following discussion
pins must be powered. Applying power to
5-21. When V
). The external RESET line remains asserted until
NOTE
DD
reaches the minimum operating
DD
ramp-up time also affects
5-55
for
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