MC9S08DZ128CLF Freescale Semiconductor, MC9S08DZ128CLF Datasheet - Page 63

• Manufacturer Part Number: MC9S08DZ128CLF
• Description: MCU 8BIT 128K FLASH 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DZ128CLF

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Package: 48LQFP
• Family Name: HCS08
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 87
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 24-chx12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Accessing either the LBP or LWP registers allows a user program to read successive memory locations
without re-writing the linear address pointer. Accessing LBP or LWP does the exact same function.
However, because of the address mapping of the registers with LBP following LWP, a user can do word
accesses in the extended address space using the LDHX or STHX instructions to access location LWP.
The MMU supports the addition of a 2s complement value to the linear address pointer without using any
math instructions or memory resources. Writes to LAPAB with a 2s complement value will cause the
MMU to add that value to the existing value in LAP2:LAP0.
4.4.3
4.4.3.1
The HCS08 Core architecture limits the CPU addressable space available to 64K bytes. The address space
can be extended to 128K bytes using a paging window scheme. The Program Page (PPAGE) allows for
selecting one of the 16K byte blocks to be accessed through the Program Page Window located at
0x8000-0xBFFF. The CALL and RTC instructions can load or store the value of PPAGE onto or from the
stack during program execution. After any reset, PPAGE is set to PAGE 2.
4.4.3.2
The three registers, LAP2:LAP0 contain the 17-bit linear address that allows the user to access any FLASH
location in the extended address map. This register is used in conjunction with the data registers, linear
byte (LB), linear byte post increment (LBP) and linear word post increment (LWP). The contents of
LAP2:LAP0 will auto-increment when accessing data using the LBP and LWP registers. The contents of
LAP2:LAP0 can be increased by writing an 8-bit value to LAPAB.
Freescale Semiconductor
XA16:XA14
Field
2:0
Reset:
MMU Registers and Control Bits
W
R
When the CPU addresses the paging window, 0x8000-0xBFFF, the value in the PPAGE register along with the
CPU addresses A13:A0 are used to create a 17-bit extended address.
Program Page Register (PPAGE)
Linear Address Pointer Registers 2:0 (LAP2:LAP0)
0
0
7
Table 4-6. Program Page Register Field Descriptions
0
0
6
Figure 4-5. Program Page Register (PPAGE)
MC9S08DZ128 Series Data Sheet, Rev. 1
5
0
0
0
0
4
Description
0
0
3
XA16
0
2
XA15
1
1
Chapter 4 Memory
XA14
0
0
63